D Programming Language 2.0

Last update Wed Aug 1 09:43:19 2012

# core.cpuid

Identify the characteristics of the host CPU, providing information about cache sizes and assembly optimisation hints. This module is provided primarily for assembly language programmers.

References:
Some of this information was extremely difficult to track down. Some of the documents below were found only in cached versions stored by search engines! This code relies on information found in:

- "Intel(R) 64 and IA-32 Architectures Software Developers Manual, Volume 2A: Instruction Set Reference, A-M" (2007).
- "AMD CPUID Specification", Advanced Micro Devices, Rev 2.28 (2008).
- "AMD Processor Recognition Application Note For Processors Prior to AMD Family 0Fh Processors", Advanced Micro Devices, Rev 3.13 (2005).
- "AMD Geode(TM) GX Processors Data Book", Advanced Micro Devices, Publication ID 31505E, (2005).
- "AMD K6 Processor Code Optimisation", Advanced Micro Devices, Rev D (2000).
- "Application note 106: Software Customization for the 6x86 Family", Cyrix Corporation, Rev 1.5 (1998)
- http://www.datasheetcatalog.org/datasheet/nationalsemiconductor/GX1.pdf
- "Geode(TM) GX1 Processor Series Low Power Integrated X86 Solution", National Semiconductor, (2002)
- "The VIA Isaiah Architecture", G. Glenn Henry, Centaur Technology, Inc (2008).
- http://www.sandpile.org/ia32/cpuid.htm
- http://www.akkadia.org/drepper/cpumemory.pdf
- "What every programmer should know about memory", Ulrich Depper, Red Hat, Inc., (2007).
- "CPU Identification by the Windows Kernel", G. Chappell (2009). http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm
- "Intel(R) Processor Identification and the CPUID Instruction, Application Note 485" (2009).

BUGS:
Currently only works on x86 and Itanium CPUs. Many processors have bugs in their microcode for the CPUID instruction, so sometimes the cache information may be incorrect.

License:
Boost License 1.0

Authors:
Don Clugston, Tomas Lindquist Olsen <tomas@famolsen.dk>

Source:
core/cpuid.d

struct CacheInfo;
  Cache size and behaviour

  size_t size;
    Size of the cache, in kilobytes, per CPU. For L1 unified (data + code) caches, this size is half the physical size. (we don't halve it for larger sizes, since normally data size is much greater than code size for critical loops).

  ubyte associativity;
    Number of ways of associativity, eg: 1 = direct mapped 2 = 2-way set associative 3 = 3-way set associative ubyte.max = fully associative

  uint lineSize;
    Number of bytes read into the cache when a cache miss occurs.

string vendor();
  Returns vendor string, for display purposes only. Do NOT use this to determine features! Note that some CPUs have programmable vendorIDs.

string processor();
  Returns processor string, for display purposes only

CacheInfo[5u] datacache;
  The data caches. If there are fewer than 5 physical caches levels, the remaining levels are set to size_t.max (== entire memory space)

@property bool x87onChip();
  Does it have an x87 FPU on-chip?

@property bool mmx();
  Is MMX supported?

@property bool sse();
  Is SSE supported?

@property bool sse2();
  Is SSE2 supported?

@property bool sse3();
  Is SSE3 supported?

@property bool ssse3();
  Is SSSE3 supported?

@property bool sse41();
  Is SSE4.1 supported?

@property bool sse42();
  Is SSE4.2 supported?

@property bool sse4a();
  Is SSE4a supported?

@property bool aes();
  Is AES supported

@property bool hasPclmulqdq();
  Is pclmulqdq supported

@property bool hasRdrand();
  Is rdrand supported

@property bool avx();
  Is AVX supported

@property bool vaes();
  Is VEX-Encoded AES supported

@property bool hasVpclmulqdq();
  Is vpclmulqdq supported

@property bool fma();
  Is FMA supported

@property bool fp16c();
  Is FP16C supported

@property bool amd3dnow();
  Is AMD 3DNOW supported?

@property bool amd3dnowExt();
  Is AMD 3DNOW Ext supported?

@property bool amdMmx();
  Are AMD extensions to MMX supported?

@property bool hasFxsr();
  Is fxsave/fxrstor supported?

@property bool hasCmov();
  Is cmov supported?

@property bool hasRdtsc();
  Is rdtsc supported?

@property bool hasCmpxchg8b();
  Is cmpxchg8b supported?

@property bool hasCmpxchg16b();
  Is cmpxchg8b supported?

@property bool hasSysEnterSysExit();
  Is SYSENTER/SYSEXIT supported?

@property bool has3dnowPrefetch();
  Is 3DNow prefetch supported?

@property bool hasLahfSahf();
  Are LAHF and SAHF supported in 64-bit mode?

@property bool hasPopcnt();
  Is POPCNT supported?

@property bool hasLzcnt();
  Is LZCNT supported?

@property bool isX86_64();
  Is this an Intel64 or AMD 64?

@property bool isItanium();
  Is this an IA64 (Itanium) processor?

@property bool hyperThreading();
  Is hyperthreading supported?

@property uint threadsPerCPU();
  Returns number of threads per CPU

@property uint coresPerCPU();
  Returns number of cores in CPU

@property bool preferAthlon();
  Optimisation hints for assembly code. For forward compatibility, the CPU is compared against different microarchitectures. For 32-bit X86, comparisons are made against the Intel PPro/PII/PIII/PM family.

  The major 32-bit x86 microarchitecture 'dynasties' have been: (1) Intel P6 (PentiumPro, PII, PIII, PM, Core, Core2). (2) AMD Athlon (K7, K8, K10). (3) Intel NetBurst (Pentium 4, Pentium D). (4) In-order Pentium (Pentium1, PMMX, Atom) Other early CPUs (Nx586, AMD K5, K6, Centaur C3, Transmeta, Cyrix, Rise) were mostly in-order. Some new processors do not fit into the existing categories: Intel Atom 230/330 (family 6, model 0x1C) is an in-order core. Centaur Isiah = VIA Nano (family 6, model F) is an out-of-order core.

  Within each dynasty, the optimisation techniques are largely identical (eg, use instruction pairing for group 4). Major instruction set improvements occur within each dynasty. Does this CPU perform better on AMD K7 code than PentiumPro..Core2 code?

@property bool preferPentium4();
  Does this CPU perform better on Pentium4 code than PentiumPro..Core2 code?

@property bool preferPentium1();
  Does this CPU perform better on Pentium I code than Pentium Pro code?

uint stepping;
  Processor type (vendor-dependent). This should be visible ONLY for display purposes.

uint model;
  Processor type (vendor-dependent). This should be visible ONLY for display purposes.

uint family;
  Processor type (vendor-dependent). This should be visible ONLY for display purposes.

Copyright Don Clugston 2007 - 2009. | Page generated by Ddoc.