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util/twi.h
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1 /* Copyright (c) 2002, Marek Michalkiewicz
2 Copyright (c) 2005, 2007 Joerg Wunsch
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright
9 notice, this list of conditions and the following disclaimer.
10
11 * Redistributions in binary form must reproduce the above copyright
12 notice, this list of conditions and the following disclaimer in
13 the documentation and/or other materials provided with the
14 distribution.
15
16 * Neither the name of the copyright holders nor the names of
17 contributors may be used to endorse or promote products derived
18 from this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE. */
31
32 /* $Id: twi.h 1196 2007-01-23 15:34:58Z joerg_wunsch $ */
33 /* copied from: Id: avr/twi.h,v 1.4 2004/11/01 21:19:54 arcanum Exp */
34
35 #ifndef _UTIL_TWI_H_
36 #define _UTIL_TWI_H_ 1
37
38 #include <avr/io.h>
39
40 /** \file */
41 /** \defgroup util_twi <util/twi.h>: TWI bit mask definitions
42 \code #include <util/twi.h> \endcode
43
44 This header file contains bit mask definitions for use with
45 the AVR TWI interface.
46 */
47 /** \name TWSR values
48
49 Mnemonics:
50 <br>TW_MT_xxx - master transmitter
51 <br>TW_MR_xxx - master receiver
52 <br>TW_ST_xxx - slave transmitter
53 <br>TW_SR_xxx - slave receiver
54 */
55
56 /*@{*/
57 /* Master */
58 /** \ingroup util_twi
59 \def TW_START
60 start condition transmitted */
61 #define TW_START 0x08
62
63 /** \ingroup util_twi
64 \def TW_REP_START
65 repeated start condition transmitted */
66 #define TW_REP_START 0x10
67
68 /* Master Transmitter */
69 /** \ingroup util_twi
70 \def TW_MT_SLA_ACK
71 SLA+W transmitted, ACK received */
72 #define TW_MT_SLA_ACK 0x18
73
74 /** \ingroup util_twi
75 \def TW_MT_SLA_NACK
76 SLA+W transmitted, NACK received */
77 #define TW_MT_SLA_NACK 0x20
78
79 /** \ingroup util_twi
80 \def TW_MT_DATA_ACK
81 data transmitted, ACK received */
82 #define TW_MT_DATA_ACK 0x28
83
84 /** \ingroup util_twi
85 \def TW_MT_DATA_NACK
86 data transmitted, NACK received */
87 #define TW_MT_DATA_NACK 0x30
88
89 /** \ingroup util_twi
90 \def TW_MT_ARB_LOST
91 arbitration lost in SLA+W or data */
92 #define TW_MT_ARB_LOST 0x38
93
94 /* Master Receiver */
95 /** \ingroup util_twi
96 \def TW_MR_ARB_LOST
97 arbitration lost in SLA+R or NACK */
98 #define TW_MR_ARB_LOST 0x38
99
100 /** \ingroup util_twi
101 \def TW_MR_SLA_ACK
102 SLA+R transmitted, ACK received */
103 #define TW_MR_SLA_ACK 0x40
104
105 /** \ingroup util_twi
106 \def TW_MR_SLA_NACK
107 SLA+R transmitted, NACK received */
108 #define TW_MR_SLA_NACK 0x48
109
110 /** \ingroup util_twi
111 \def TW_MR_DATA_ACK
112 data received, ACK returned */
113 #define TW_MR_DATA_ACK 0x50
114
115 /** \ingroup util_twi
116 \def TW_MR_DATA_NACK
117 data received, NACK returned */
118 #define TW_MR_DATA_NACK 0x58
119
120 /* Slave Transmitter */
121 /** \ingroup util_twi
122 \def TW_ST_SLA_ACK
123 SLA+R received, ACK returned */
124 #define TW_ST_SLA_ACK 0xA8
125
126 /** \ingroup util_twi
127 \def TW_ST_ARB_LOST_SLA_ACK
128 arbitration lost in SLA+RW, SLA+R received, ACK returned */
129 #define TW_ST_ARB_LOST_SLA_ACK 0xB0
130
131 /** \ingroup util_twi
132 \def TW_ST_DATA_ACK
133 data transmitted, ACK received */
134 #define TW_ST_DATA_ACK 0xB8
135
136 /** \ingroup util_twi
137 \def TW_ST_DATA_NACK
138 data transmitted, NACK received */
139 #define TW_ST_DATA_NACK 0xC0
140
141 /** \ingroup util_twi
142 \def TW_ST_LAST_DATA
143 last data byte transmitted, ACK received */
144 #define TW_ST_LAST_DATA 0xC8
145
146 /* Slave Receiver */
147 /** \ingroup util_twi
148 \def TW_SR_SLA_ACK
149 SLA+W received, ACK returned */
150 #define TW_SR_SLA_ACK 0x60
151
152 /** \ingroup util_twi
153 \def TW_SR_ARB_LOST_SLA_ACK
154 arbitration lost in SLA+RW, SLA+W received, ACK returned */
155 #define TW_SR_ARB_LOST_SLA_ACK 0x68
156
157 /** \ingroup util_twi
158 \def TW_SR_GCALL_ACK
159 general call received, ACK returned */
160 #define TW_SR_GCALL_ACK 0x70
161
162 /** \ingroup util_twi
163 \def TW_SR_ARB_LOST_GCALL_ACK
164 arbitration lost in SLA+RW, general call received, ACK returned */
165 #define TW_SR_ARB_LOST_GCALL_ACK 0x78
166
167 /** \ingroup util_twi
168 \def TW_SR_DATA_ACK
169 data received, ACK returned */
170 #define TW_SR_DATA_ACK 0x80
171
172 /** \ingroup util_twi
173 \def TW_SR_DATA_NACK
174 data received, NACK returned */
175 #define TW_SR_DATA_NACK 0x88
176
177 /** \ingroup util_twi
178 \def TW_SR_GCALL_DATA_ACK
179 general call data received, ACK returned */
180 #define TW_SR_GCALL_DATA_ACK 0x90
181
182 /** \ingroup util_twi
183 \def TW_SR_GCALL_DATA_NACK
184 general call data received, NACK returned */
185 #define TW_SR_GCALL_DATA_NACK 0x98
186
187 /** \ingroup util_twi
188 \def TW_SR_STOP
189 stop or repeated start condition received while selected */
190 #define TW_SR_STOP 0xA0
191
192 /* Misc */
193 /** \ingroup util_twi
194 \def TW_NO_INFO
195 no state information available */
196 #define TW_NO_INFO 0xF8
197
198 /** \ingroup util_twi
199 \def TW_BUS_ERROR
200 illegal start or stop condition */
201 #define TW_BUS_ERROR 0x00
202
203
204 /**
205 * \ingroup util_twi
206 * \def TW_STATUS_MASK
207 * The lower 3 bits of TWSR are reserved on the ATmega163.
208 * The 2 LSB carry the prescaler bits on the newer ATmegas.
209 */
210 #define TW_STATUS_MASK (_BV(TWS7)|_BV(TWS6)|_BV(TWS5)|_BV(TWS4)|\
211 _BV(TWS3))
212 /**
213 * \ingroup util_twi
214 * \def TW_STATUS
215 *
216 * TWSR, masked by TW_STATUS_MASK
217 */
218 #define TW_STATUS (TWSR & TW_STATUS_MASK)
219 /*@}*/
220
221 /**
222 * \name R/~W bit in SLA+R/W address field.
223 */
224
225 /*@{*/
226 /** \ingroup util_twi
227 \def TW_READ
228 SLA+R address */
229 #define TW_READ 1
230
231 /** \ingroup util_twi
232 \def TW_WRITE
233 SLA+W address */
234 #define TW_WRITE 0
235 /*@}*/
236
237 #endif /* _UTIL_TWI_H_ */

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