Newsgroups: comp.lsi,comp.lsi.cad,news.answers,comp.answers Path: senator-bedfellow.mit.edu!bloom-beacon.mit.edu!spool.mu.edu!agate!news.ucdavis.edu!altarrib!hemlock From: altarrib@hemlock.ece.ucdavis.edu (Michael Altarriba) Subject: comp.lsi.cad Frequently Asked Questions With Answers (Part 4/4) [LONG] Message-ID: Followup-To: comp.lsi.cad Summary: This is a biweekly posting of frequently asked questions with answers the for comp.lsi / comp.lsi.cad newsgroups. It should be consulted before posting questions to comp.lsi or comp.lsi.cad. Keywords: FAQ Sender: usenet@ucdavis.edu (News Administrator) Supersedes: Reply-To: clcfaq@eecs.ucdavis.edu Organization: Department of Electrical and Computer Engineering, UC Davis References: Date: Fri, 20 Aug 1993 23:03:04 GMT Approved: news-answers-request@MIT.Edu Lines: 671 Xref: senator-bedfellow.mit.edu comp.lsi:3072 comp.lsi.cad:3354 news.answers:11629 comp.answers:1677 Archive-name: lsi-cad-faq/part4 a palette picture file that displays all 52 symbols in a compact grid that you can cut and paste from within TeXcad. Each symbol lives in its own .mac file and is defined as a 'savebox' so as to reduce memory con- sumption. You must add the [bezier] option to your 'documentstyle' com- mand. A small manual is provided in both Postscript and .dvi forms. The files lcircuit.zip and lcircuit.tar are available for anonymous ftp from cscx.cs.rhbnc.ac.uk (134.219.200.45) in directory pub/lcircuit. I will also be uploading them to various ftp servers in the coming week. 46: Tanner Research Tools (Ledit and LVS) (From Bhusan Gupta ) Low cost, yet very powerful commercial ASIC design tools are available from Tanner Research, Inc. in Pasadena, CA. These products are used by industry and universities alike. Tanner's products are nominally priced at $995 per program, with a combined package named L-Edit Pro available for $3,495 on the PC. Universities are offered a 75% discount. Here is a list of their current programs: L-EditTM : A full-custom layout editor with CIF and GDSII input/output. Features a 32-bit coordinate space, all-angle geometry, unlimited hierarchy and number of layers. The L-Edit Pro package includes L-Edit/DRC for design rule checking, L-Edit/SPR for automatic standard cell placement and routing, L-Edit/Extract for extracting transistors, capacitors, resistors and generic devices for SPICE-level simulation or comparison to a schematic and LVS ,a netlist comparison tool for topological and parametrical verification. Optional layout libraries are also available. T-Spice: Circuit level simulator (See item 41 for detail GateSimTM : Gate-level simulator. A full array of technology mapping libraries are also available. Products are available for the PC, Macintosh, Sun and Hp UNIX platforms. For more information contact Bhushan Mudbhary at Tanner Research (bhushan @ tanner.com), phone 818-792-3000 and fax 818-792-0300. 47: SIMIC, a full-featured logic verification simulator. (From comp.archives.msdos.announce) SIMIC is a full-featured logic verification simulator. It has been demonstrated that SIMIC can uncover a number of critical design errors that other simulators miss. SIMIC has shown superior accuracy and throughput when compared to competitive products. Here are some of SIMIC's important features: - Mixed-mode simulation allows the free intermixture of true bilateral switches (ideal and resistive), gate, plus functional level built-in and user defined primitives. - A wide variety of output, whose detail, content and format are, to large extent, user defined. - A large repetoire of simulation options and controls that can be applied interactively, or in batch operation, and simplify trouble-shooting of your design. - Automated Test equipment emulation, allows debugging test programs using SIMIC troubleshooting techniques. - Sophisticated hazard analysis including: Spike, Pulse, Conflict, Oscillation, Setup, Hold, Pulse-width, Near (what-if) detection, among others. Hazard propagation is also supported. The student version of SIMIC is limited to a maximum of 500 elements (parts). In all other respects it is the same program as the commercial offering. The PC student version requires a 386 or better and at least 2 Meg of memory. Both a DPMI and a VCPI version are included in the pack- age. Both versions require EMS *NOT* be disabled. SIMIC is also avail- able on Sun and other platforms. 48: LASI CAD System, IC and device layout for IBM compatibles (from Mike Fitsimmons ) On behalf of the author I have uploaded to WSMR-SIMTEL20.Army.Mil: pd1: LASI41A.ZIP LASI v4.1 IC layout CAD prgm: unzip in LASI41B.ZIP LASI v4.1 IC layout CAD prgm: unzip in LASI41C.ZIP LASI v4.1 IC layout CAD prgm: unzip in LASIDEMO.ZIP LASI v4.1 DEMO drawing: unzip in The LASI CAD System has been developed to do integrated circuit and dev- ice layout on almost any IBM compatable personal computer. LASIDEMO is a small IC layout to be used as a demonstration when first learning to use LASI. I offered to pay the author for some sort of site license for this pro- gram, but he refused, saying that he actually wants educational institu- tions to use it for free. What a guy! 49: EEDRAW, an electrical/electronic diagramming tool for IBM compatibles (from ) I have uploaded to WSMR-SIMTEL20.Army.Mil: pd1: EEDRAW24.ZIP Electrical Engineering drawing (with layers) This is the 2.4 release of EEDRAW, an electrical/electronic diagramming tool for the IBM PC. pd1: EEDSRC24.ZIP C sources for EEDRAW24.ZIP program. TC/BC++ This is the source of the EEdraw 2.4 program. Please read the readme file in the primary archive for information on other source programs needed such as the Libary files. 50: MagiCAD, GaAs Gate Array Design through MOSIS (from Tom Smith ) The Mayo Graphical Integrated Computer Aided Design (MagiCAD) system is a package which provides a comprehensive design environment for the development of digital systems, from initial concept to post-layout verification of integrated circuits (ICs). MagiCAD focuses on the development of high-speed Gallium Arsenide (GaAs) gate array designs. Specialized electromagnetic simulation tools are provided to address high clock rate issues such as crosstalk and reflections, which become more important as clock rates exceed several hundred MHz or signal edge rates become less than 500 pico- seconds. MagiCAD provides all the necessary tools for high clock rate GaAs IC design, and is also integrated with non-Mayo circuit, logic, and fault simulators. MagiCAD provides a lower risk approach than full-custom design for universities wishing to perform digital GaAs design through MOSIS. This is done by providing a gate array design environment where low-level transistor design and layout issues have already been solved and abstracted into a technology library of pre-defined cells. This frees the student or researcher to solve the still challenging tasks of system and gate-level design and layout to get high clock rate chips fabricated through MOSIS that meet all specifications. MagiCAD supports hierarchical, top-down, middle-out, or bottom-up development styles. MagiCAD has been used in the design of many GaAs chips that have been successfully fabricated. The MagiCAD electromagnetic modeling tools have been used in the analysis of many actual packages, multi-chip modules (MCMs), and printed circuit boards (PCBs), uncovering and avoiding problems that are commonly associated with high-frequency, fast edge-rate designs. The Vitesse Fury (TM) GaAs VSC2K gate array is provided as a MagiCAD technology library, and has been used for both gra- duate and undergraduate student chip designs. Functionality that has been integrated into MagiCAD includes: o Vitesse VSC2K GaAs gate array technology library o Database which integrates all tools o Schematic entry through a general purpose graphics editor o Circuit simulator o Logic and timing simulators o Fault analysis o Place and route tools o Layout verification tools o Retargeting from generic design to specific technology o Output to standard GDSII format for mask creation o Electromagnetic analysis - Cross section entry with graphics editor - Multilayer multiconductor transmission line (MMTL) modeling - Network tool for solving cases with many transmission line components - Lossy and non-lossy cases - Frequency and time domain result displays - Used for analyzing complex design paths, through chip, MCM, and PCB The Vitesse VSC2K has the following characteristics: o HGaAs-2 (TM) process o 2700 available gates o Enhancement/depletion MESFET process o 80 signal pads o 2 GHz flip-flop toggle rates o 40 power, ground pads o 280 psec loaded gate delays o 2.4 watts maximum o 170 mils x 135 mils o ECL or TTL I/O o 132 pin LDCC package available o 2 routing layers The Mayo Foundation has used MagiCAD to design several VSC2K designs that have been fabricated through both MOSIS and Vitesse. These designs have measured operating frequencies of 500 MHz to 1 GHz, depending upon the section of the circuit being tested. The general application thrust of these designs has been components which are being used to evaluate MCM technologies for high speed systems, as well as high speed data genera- tion and acquisition circuits. The University of Wisconsin - Milwaukee has used MagiCAD to design several VSC2K designs that have been fabricated through MOSIS. These designs have simulated clock rates from 100 MHz to 600 MHz. The general application thrust of these designs has been components of digital signal processors with medical image processing applications. The descriptions of these VSC2K personalizations that have been designed and fabricated include: o 8-bit Booth's algorithm multiplier o 4-bit arithmetic logic unit o 8-bit combinatorial multiplier o 24-bit carry look-ahead adder The Defense Advanced Research Projects Agency (DARPA) has authorized and funded Mayo to supply MagiCAD to universities in the U.S. for research and educational purposes. The direct cost to the universities for the MagiCAD software itself is zero (although there may be costs for any non-Mayo software that universities may want, as well as possible costs to get the proper hardware/software platform). Mayo-supplied MagiCAD training and support costs to these institutions is funded by DARPA, and is therefore free to the universities. While the MagiCAD tools are presently only available for VAX/VMS environ- ments, work is presently underway to port MagiCAD to POSIX-compliant platforms (POSIX is the IEEE "UNIX-like" portable operating system defin- ition). First POSIX platforms presently planned to port to include DECs- tations and HP workstations, likely availability of MagiCAD on these platforms is second half of 1993. The general steps for a university to begin using MagiCAD for digital GaAs gate array design include: 1) Contact Mayo Foundation to acquire MagiCAD software 2) Contact MOSIS to acquire general MOSIS information and Vitesse-specific technology information. Point Of Contact For Acquiring MagiCAD And MagiCAD Support: Thomas J. Smith Mayo Foundation Special Purpose Processor Development Group 200 First St. S. W. Rochester, Minnesota 55905 Telephone: (507) 284-0840 Telefax: (507) 284-9171 EMail: tsmith@mayo.edu Point Of Contact For Acquiring General MOSIS Information And Vitesse-specific Technology Information: Sam Reynolds The MOSIS Service USC/ISI 4676 Admiralty Way Marina del Rey, CA 90292-6695 Telephone: (310) 822-1511 x172 Telefax: (310) 823-5624 EMail: sdreynolds@mosis.edu 51: XSPICE, extended version of Spice (from Jeff Murray ) I am one of the developers of XSPICE, and at the risk of being deluged with requests for specific information on the tools, I can volunteer to answer at least some questions. Currently there is no ftp site for infor- mation; if there were, this posting would likely be unnecessary. However, we are prohibited from posting even the User's Manual due to technology export restrictions. The following is a copy of the original press release on XSPICE. If anyone would like additional clarification beyond this, or if some aspects of the release are unclear, we can certainly take this as an opportunity to remedy the situation. Please note that at the current time there are many dozens of individuals who have obtained a copy of the tools; if they have any comments or observations to make, I'm sure they would be most welcome to other members of the user community. XSPICE Press Release January 2, 1993 Georgia Tech Research Corporation XSPICE, introduced at the 1992 International Symposium on Circuits and Systems (ISCAS), is an extended and enhanced version of the popular SPICE analog circuit simulation program originally developed at the University of California at Berkeley. XSPICE was developed at the Georgia Tech Research Institute (GTRI) as a tool for simulating circuits and systems at multiple levels of abstraction. XSPICE permits a user to simulate ana- log, digital, and even non-electronic designs from the circuit level through the system level in a single simulator. A special Code Modeling feature allows users to add new models directly into the simulator exe- cutable for maximum simulation speed and accuracy. Code models are writ- ten in the C programming language allowing arbitrarily complex behavior to be described. Code model development tools are provided to simplify the process of creating new models, compiling them, and linking them with the XSPICE core. XSPICE provides a rich set of predefined code models in addition to the standard discrete device models available in SPICE. The XSPICE code model library contains over 40 new functional blocks including summers, multi- pliers, integrators, magnetics models, limiters, S-domain transfer func- tions, digital gates, digital storage elements, and a generalized digital state-machine. Digital functions are simulated in XSPICE through an embedded event- driven algorithm added to the SPICE core. This algorithm is coordinated with the analog simulation algorithm to provide fast and accurate simula- tion of mixed-signal circuits and systems. The event-driven algorithm supports a new "User-Defined Node" capability allowing additional event- driven data types to be defined and used. XSPICE comes with a 12-state digital data type as well as a user-defined node library that includes 'real' and 'integer' types useful in simulating sampled-data systems such as Digital Signal Processing algorithms. XSPICE is currently available for UNIX workstations and is supplied in source code form allowing users to customize and extend the simulator and models to particular needs. To date, the simulator has been successfully compiled and used on HP Apollo and Sun workstations. The XSPICE simulator and User's Manual are available with a cost-free license arrangement from the Georgia Tech Research Corporation for a distribution charge of US $200 (including first class postage within the U.S.A.; an additional US $25 is required for overseas delivery by air). For further information, please contact the Office of Technology Licensing, Georgia Tech Research Corporation, Georgia Institute of Technology, 400 Tenth Street, Atlanta, GA 30332-0415, USA, or phone (404) 894-6287 (voice) or (404) 894-9728 (FAX). Internet users may send email to XSPICE@GTRI.GATECH.EDU to obtain copies of the order form and license agreement (please include the word "license" in the subject header when mailing to this address). 52: MISIM, a model-independent circuit simulation tool (from Bardo Muller ) University of Washington has recently released the updated MISIM simula- tor. The new release (Sun version) is now available through ftp with anonymous login. The node address is 128.95.31.10. The release is under /pub/misim.SUN.2.3.a. If you have any question, please don't hesitate to contact us (misim_support@ee.washington.edu). Or, you can contact Prof. Andrew Yang at 206-543-2932. Attention: --------- We are currently re-writing the whole MISIM system in C with broader design consideration. The noise and temperature simulation capability will be incorporated into our next release. It would have more flexible front end with better simulation performance. The new version is expected sometime around the end of this summer. Since the actual release no longer reflected the level of our technology, we removed it from our ftp directory. MISIM Development Team Department of Electrical Engineering University of Washington MISIM 2.3A Release: General Information ------------------------------------------ A) New capabilities: ---------------- MISIM 2.3A is distinguishable from the previous release in that is now integrates a transistor-level mixed analog-digital simulator based on analytical digital macromodeling. The mixed-signal simulator is equipped with a front-end translator which accepts standard SPICE netlist syntax and converts it into MISIM mixed-mode syntax. Analytic macromodels for digital subcircuits are generated and loaded into MISIM core simulator automatically. Synchronized simulation is then performed for the digital subcircuits (processed by analytic solution) and the analog subcircuits (processed by proven analog simulation algorithms) with much accelerated speed and superior analog accuracy ( within 3-5 % of SPICE). The MISIM mixed-signal simulator supports all standard Berkeley MOS model (Level 1, 2, 3, BSIM 1, BSIM 2). User-defined MOS models of arbitrary complexity are also supported. Currently, the procedure of processing analytic digital macromodeling cannot be applied to bipolar devices (G-P model). Hence, all bipolar transistors will be simulated as "analog" components. MISIM's X-window graphic environment, WISE, has been upgraded to support the mixed-signal simulation capabilities. B) Model Improvements: ------------------ MISIM 2.3A now supports improved SPICE models (MOS, Diode, BJT). Many of the model discontinuities have been resolved leading to more reliable simulation. The MOS Level 2 and Level 3 models have also been upgraded to an improved charge-conserved models. The standard SPICE diode model has been enhanced to a non-quasi-static model capable of simulating accu- rately the diode recovery effect. These improved SPICE models are released as linked models. Users are not recommeded to unload these improved models. C) A New Parser: ------------ MISIM 2.3A incorporates a new netlist parser which supports two different modes: 1) Standard SPICE netlist syntax - default mode. 2) Enhanced SPICE net- list syntax - MISIM mode. This new capability is designed to make MISIM completely spice- compatible. In addition, the new parser now handles symbolic names and expressions. D) Updated Documentations: ---------------------- An updated MISIM User's guide is available in postcript form. On-line documentations is also provided. E) Future Release (MISIM 3.0): -------------------------- 1) The next release will include a new C-version analog simulator which has been benchmarked to be a factor of 2 to 3 times faster than the current fortran version. 2) The mixed-signal simulator will be enhanced to improve digital cover- age rate (percentage of a mixed A/D circuit which can be processed by the analytic digital macromodel) for better simulation performance. 53: Nelsis Cad Framework (from their 'README' file) Release 4.3 is the latest version of the Nelsis IC Design System. It contains a CAD framework that puts a substantial added-value under the fingertips of the designer by organizing the design information and keeping track of the design evolution. It permits integration of tools of different origin and achieves run-time efficiency. The framework is based on intelligent management of meta data on top of the actual design descriptions; it administers high level information about the design activities and the structure and status of the design, rather than operating at the level of the detailed design descriptions. The framework services, such as flow management, version manage- ment, concurrency control and state management, have been implemented on top of the meta data management module. The framework controls access to the design objects and administers meta data by performing OTO-D queries. Tools operate on top of the framework via the Data Management Interface, obtaining access to the design data according to a nested transaction schema. The Nelsis CAD Framework is available, together with a set of design tools for demonstration purposes, through anonymous ftp from dutente.et.tudelft.nl (130.161.144.6), in /pub/nelsis. 54: APLAC, a system-level simulator and IEEE-488 measurement tool (from Sakari Aaltonen ) ----------------------------------------- APLAC 6.1 ----------------------------------------- General information APLAC, a program for circuit simulation and analysis, is a joint develop- ment of the Circuit Theory Lab of Helsinki University of Technology and Nokia Corporation's Research Center. The main analysis modes are DC, AC, noise, transient, oscillator, and (multitone harmonic) steady state. APLAC can also be used for measurements with IEEE-488 apparatus. APLAC's transient analysis uses convolution for correct treatment of components with frequency-dependent characteristics. Monte Carlo analysis is avail- able in all basic analysis modes, as is sensitivity analysis in DC and AC modes. N-port Z, Y, and S parameters, as well as two-port H parameters, can be used in AC analysis. APLAC also includes a versatile collection of system level blocks for the simulation and design of analog and digital communication systems. Component models Too many to be listed here. In addition to familiar Spice models, a great number of microwave components (microstrip/stripline) are included. Sys- tem models include formula-based and discrete-time models useful in RF design. The model parameters of the components may have any functional dependency on frequency, time, temperature, or any other parameter. Users can create new components by defining their - possibly nonlinear - static and dynamic characteristics in APLAC's interpreter-type language. Spice- syntax models can be imported. Input APLAC reads its input - the nodes, branches, and model parameters of the components - from a text file. Model libraries can be created and included. Expressions are written in a program-like manner; user func- tions may be defined. Conditional and looping control structures are sup- ported. Output The output results from one or several sweeps of any user-defined func- tion of the circuit parameters, time, frequency, or temperature. The results may be printed or plotted in rectangular or polar coordinates, or on the Smith chart. Graphics output can be directed to an HPGL- or CSDF- type file, or to a graphics file for later viewing. Optimization APLAC includes several optimization methods: gradient, conjugate gra- dient, minmax, random, simulated annealing, tuning (manual optimization) and gravity center (design centering). Any parameter in a design problem can be used as a variable and any user-defined function may act as an objective. Machine environment Unix: X11; PC: MS-Windows (math coprocessor required). Contact information ------------------- Martti Valtonen Heikki Rekonen Helsinki University of Technology Nokia Research Center Circuit Theory Laboratory Hardware Design Technology Otakaari 5A, SF-02150 Espoo, FINLAND P.O.Box 156, SF-02101 Espoo, FINLAND Fax: 358-0-460224 Tel: 358-0-43761 e-mail:martti@aplac.hut.fi Fax: 358-0-455 2557 Free (university version) binaries for HP9000/700, Sun4, and PC machines are available via FTP from nic.funet.fi:/pub/cae/aplac. Help files, PS manuals, and collections of APLAC examples are in the same directory. 55: SLS, a switch-level simulator (from comp.lsi.cad) DELFT UNIVERSITY OFFERS UNIQUE SWITCH-LEVEL SIMULATOR SLS is a switch-level simulator that can be used to simulate the logic and timing behavior of large digital circuits that are described at the (mixed) MOS transistor, gate and functional level. It has fast and accu- rate algorithms to predict the timing behavior of MOS circuits containing > 100,000 transistors. MOS transistor-level circuit descriptions are easily mixed with gate-level and functional-level circuit descriptions, where the behavior of the latter are described in the C programming language. There is an X-window based user-interface to graphically edit the input signals and to inspect the simulation output signals. The same interface is used to alternatively simulate the circuit with the well- known circuit simulator SPICE. SLS has already been used by many people at many different sites, and numerous chips have been designed with it. SLS is now made available world-wide to serve as a useful design and verification tool to the international design community. Apart from being used as a stand-alone tool, SLS can also be used as a part of the popular design system for Sea-Of-Gates circuits OCEAN, or it can be con- nected to the advanced Nelsis CAD framework. The SLS simulator has three different simulation levels: 1. Purely logic simulation based on abstract transistor strengths: This level more or less behaves similar to the original switch-level model as proposed by R.E. Bryant. It computes logic states by only considering node states and transistor types. 2. Logic simulation based on exact transistor dimensions and node capacitances: This level uses resistance division and capacitance division algorithms to compute logic states. It finds correct logic states in much more situations than conventional switch-level simulators, e.g. when a resistance division occurs between a saturated transistor and a non-saturated transistor. 3. Logic and timing simulation based on transistor and node parameters: RC time constant evaluations are used to approximate real voltages by PIECEWISE-LINEAR VOLTAGE WAVEFORMS. This not only provides delay times for the circuit, but is also delivers an accurate representation for transient effects like spikes and races. Apart from electrical network elements like MOS transistors, resistors and capacitors, an SLS network may contain (i) gate primitives like inverters, nands, nors, etc. and (ii) user-defined function blocks like roms, shiftregisters, multipliers. The behavior of function blocks is described by the user in the C programming language: it is specified by the user how the values of the output terminals and the state variables are computed from the values of the input terminals and the state vari- ables. For more information about SLS, see, "Switch-level timing simulation," P.M. Dewilde, A.J. van Genderen, A.C. de Graaf, Proc. ICCAD 85 Conf., Santa Clara, Nov. 1985, pp. 182-184 "SLS: An Efficient Switch-Level Timing Simulator Using Min-Max Voltage waveforms," A.J. van Genderen, Proc. VLSI 89 Conf., Munich, Aug. 1989, pp. 79-88. "SLS: Switch-Level Simulator User's Manual," A.C. de Graaf, A.J. van Genderen, Delft University of Technology (available for ftp at the address below). Availability: SLS is written in C and runs under UNIX and X-windows. It runs, among other things, on Sun SPARC stations, HP 9000 series 700/800 machines, and PCs running Linux. The program is available for free under the terms of the GNU General Public License. It can be retrieved via anonymous ftp from the directory pub/sls on dutentb.et.tudelft.nl. It is also possible to obtain SLS as a part of the OCEAN system for the design of Sea-Of-Gates circuits. This system can be obtained from the directory pub/ocean on donau.et.tudelft.nl. The OCEAN system among other things contains a layout-to-circuit extractor that can extract large lay- outs and that stores the result directly in the database that is read by SLS. Furthermore, SLS is available as a tool in the Nelsis CAD framework from the directory pub/nelsis on dutente.et.tudelft.nl. The latest ver- sion of SLS can always be found on dutentb.et.tudelft.nl. For questions, remarks and bug reports, contact Arjan van Genderen Delft University of Technology Department of Electrical Engineering Mekelweg 4 phone: 31-15-786258 2628 CD Delft fax: 31-15-623271 The Netherlands email: arjan@dutentb.et.tudelft.nl 56: OCEAN, a sea-of-gates design system (from Patrick Groeneveld ) About OCEAN: the sea-of-gates design system ------------------------------------------- OCEAN is a comprehensive chip design package which was developed at Delft University of Technology, the Netherlands. It includes a full set of powerful tools for the synthesis and verification of semi-custom sea-of- gates and gate-array chips. OCEAN covers the back-end of the design tra- jectory: from circuit level, down to layout and a working chip. In a nut- shell, OCEAN has the following features: + Available for free, including all source code. + Short learning curve making it suitable for student design courses. + Hierarchical (full-custom-like) layout style on sea-of-gates. + Powerful tools for placement, routing, simulation and extraction. + Any combination of automatic and interactive manual layout. + OCEAN can handle even the largest designs. + Running on popular HP, Sun and 386/486 PC machines, easy installation. + Includes three sea-of-gates images with libraries and a 200,000 transistor sea-of-gates chip. + Can be easily adapted to arbitrary images with any number of layers. + Interface programs for other tools and systems (SIS, cadence, etc.) + Robust and 'combat-proven', used by hundreds of people. How to retrieve OCEAN and additional documentation? --------------------------------------------------- The entire OCEAN system is available for free via anonymous ftp, gopher or on tape. A powerful installation script is included, so you can get started very quickly without hacking up the code. You can retrieve OCEAN and additional documentation via: anonymous ftp: donau.et.tudelft.nl - directory pub/ocean gopher: olt.et.tudelft.nl (port 70) or use the path World --> Europe --> Netherlands --> Delft University of Technology Electronic Engineering --> Research activities --> The OCEAN sea-of-gates Design System We advise to retrieve first the documents with the user manual. (The file 'ocean_docs.tar.gz'). If you have any questions, remarks or problems, just contact us: Patrick Groeneveld or Paul Stravers Electronic Engineering Group, Electrical Engineering Faculty Delft University of Technology Mekelweg 4, 2628 CD Delft The Netherlands Phone: +31-15786240 Fax: +31-15786190 Email: ocean@donau.et.tudelft.nl