gtpm2m39Migration Guide: Program Update Tapes

32-Way Loosely Coupled Processor Support (APAR PJ27785)

The following section discusses the migration considerations for 32-way loosely coupled processor support.

Prerequisite APARs

See the APEDIT for APAR PJ27785 for information about prerequisite APARs.

Functional Overview

32-way loosely coupled processor support provides the additional capacity needed to support application workload growth by allowing as many as 32 processors in a loosely coupled complex. The functions necessary to provide this capability have been implemented over several program update tape (PUT) releases. This release provides the functions necessary to make this support a reality.

The following functional areas and constraints are addressed:

Coexistence

To ease migration to 32-way loosely coupled processors, processors running with 32-way loosely coupled processor support and processors running at a back-level of support can coexist in the same loosely coupled complex. When operating in coexistence mode, you must observe the following restrictions:

Migration and Fallback

When migrating to 32-way loosely coupled processor support, you must observe the following considerations and restrictions:

After you have migrated to 32-way loosely coupled processor support, but have not yet added a ninth processor to the loosely coupled complex, you can fall back to a TPF 4.1 system image without 32-way loosely coupled processor support on one or more processors in the complex. If you do, be aware of the following:

See Falling Back from 32-Way Loosely Coupled Processor Support for more information about the steps required for falling back.

Architecture

A number of functions and data structures were modified and enhanced to support 32-way loosely coupled processors. The following describes the design considerations for these changes.

Data Structures

A number of fields and data structures that are used throughout the TPF 4.1 system are limited to an 8-way loosely coupled processor complex. Many of these fields and structures use 1-byte bit masks to represent the processors in the complex. The following describes the changes to the data structures and fixed file record formats to support 32-way loosely coupled processors:

MPIF Hardware Definition Record
This record is currently supported using the #CB8HD fixed file record. The CB8CONx field in this record needs to be expanded to 32 bytes, increasing the item length for each hardware definition record to 64 bytes (including spare bytes for future expansion). The increased item length results in the requirement for additional records to hold the hardware definitions.

To ease migration, record type #HDREC has been created to support the increased data size and number of records. The hardware definitions are copied to the new record type the first time a processor with 32-way loosely coupled processor support is IPLed.

In coexistence mode, processors running a back-level TPF 4.1 system continue to access the old records. Once migration is completed and there is no requirement to run a back-level processor, the #CB8HD records are removed from the TPF 4.1 system.

MPIF Path Definition Record
The path definition record is currently maintained in processor shared #PDREC records. The first two of these records, ordinals 0 and 1, hold shared information about the processors while the remaining ordinals are assigned to unique processors in order. The 32-way loosely coupled processors increase both the number of processor unique records required and the possible number of path combinations between processors.

Because most of the data is processor unique and to ease migration, the processor unique information has been moved to a new record type, #PDREU. The processor shared information remains in ordinals 0 and 1 of the #PDREC records. When an existing processor is IPLed for the first time with 32-way loosely coupled processor support, the processor unique data for that processor is migrated from the #PDREC record type to the #PDREU record type. When a new processor is added to the loosely coupled complex, the operator is prompted to enter the ZMPIF PDR INIT command during TPF 4.1 system restart. This command will initialize the #PDREU data for the new processor.

In coexistence mode, processors running a back-level TPF 4.1 system continue to access the old records. Once migration is completed, #PDREC ordinals 2 and 3 are used for future expansion of processor shared information and ordinals 4 and higher should be removed from the TPF 4.1 system.

INETD Configuration File (IDCF)
The IDCF currently uses four #IBMM4 fixed file records, ordinals 158 - 161. With 32-way loosely coupled processors, each processor would be limited to three entries in the table. This is too few and, with the amount of expansion required, record type #IDCF1 was created to hold this information.

The first time a ZINET command is entered that accesses the #IDCF1 record type, the data is moved from the old records to the new record type. Subsequently, any processor that is IPLed with 32-way loosely coupled processor support will access the new IDCF record type.

In coexistence mode, processors running a back-level TPF 4.1 system continue to access the old records. Once migration is completed, the #IBMM4 records that contain the old IDCF information can be set to zero to avoid future error conversions.

CLAW Device Table (CDT) and TCP/IP Configuration Table (ITCPC)
The CDT currently uses eight #IBMM4 fixed file records (ordinals 109 - 116) that are indexed by processor ordinal, and the ITCPC uses eight #IBMM4 fixed file records (ordinals 150 - 157) that are indexed by processor ordinal. With 32-way loosely coupled processors, these tables have been moved to #IBMMP4 processor unique records.

If CLAW support and TCP/IP support are defined in the TPF 4.1 system, the CDT and ITCPC records are moved to the #IBMMP4 records the first time an existing processor is IPLed with 32-way loosely coupled processor support. For a new processor being added to the loosely coupled complex, the CDT and ITCPC records are initialized the first time the TPF 4.1 system is IPLed.

In coexistence mode, processors running a TPF 4.1 system without 32-way loosely coupled processor support continue to access the CDT and ITCPC in the #IBMM4 records.

RCAT Initialization (RCIT) Record
The current RCIT record has a 1-byte field, RC1FLD, that is used as a switch to determine if a processor needs to do a fresh load of the routing control application table (RCAT). With 32-way loosely coupled processor support, this field has been moved to the end of the RCIT record and expanded to 4 bytes so that it can support 32-way loosely coupled processors.

Node Control Block (NCB)
The current NCB uses a 1-byte bit mask to represent processors. With 32-way loosely coupled processor support, this field has been expanded to 4 bytes using reserved space in the record. Because of the large number of entries, the NCBs will be migrated as they are used and the TPF 4.1 system will update both fields.

SNA Dynamic Resource Definition
Currently there are six 1-byte bit masks used to represent processors. With 32-way loosely coupled processor support, these fields have been expanded to 4 bytes each using reserved space in the record. Four of the masks (DLRIND5, DLRIND6, DLRIND7, and DRLFLBK) have been expanded in place; two others (DLRIND2 and DLRPREV) have been moved to an area in the record with available space.

Keypoint I (CTKI)

CTKI currently maintains a table of cycle indicators called a subsystem state table (SST) at tag IC0SST. This table is defined by data macro CN1ST. To expand this table to support 32-way loosely coupled processors, the data has been moved to FACE fixed file record type #CN1ST, with 64 ordinals. Segment CYYF has been created, similar to CYYA and CYYM, to handle file input and output for the new records. When the loosely coupled complex is operating in coexistence mode, segment CYYF supports access to the old subsystem state table in CTKI by processors with 32-way loosely coupled processor support installed by accessing the data in CTKI and reformatting it so that it appears to be in 32-way loosely coupled format.

Keypoint C (CTKC)

CTKC maintains a table of terminals used in the TPF complex. To expand this table for 32-way loosely coupled processors, the CK8KE macro and the data in CTKC have been expanded. Segments CYYK and CYYL have been added and are called by segments CYYA and CYYM to handle file input and output for CTKC. When the loosely coupled complex is operating in coexistence mode, CTKC (including the CK8KE macro) is loaded in main storage and formatted to 32-way loosely coupled format. CTKC and CK8KE are formatted back to 8-way loosely coupled format before being filed.

General File

General file support currently uses one ordinal from the #IBMM4 record type for each processor in the TPF complex to hold the associated general file control record (GFCR). #IBMM4 records, ordinal numbers 101 - 108, are used to support the current maximum 8-way loosely coupled complex. With 32-way loosely coupled processor support, the GFCR is allocated as a single ordinal number (29) in processor unique record type #IBMMP4.

Migration to the #IBMMP4 processor unique record type occurs during general file restart. Each processor migrates or initializes only its own records. General file restart does the following:

  1. If keypoint B is loaded and indicates that the GFCR should be loaded from premounts, the GFCR in the #IBMMP4 record is initialized from the premount record in segment CVZD.
  2. If the GFCR was not initialized from the premount record and a record ID (RID) or record control check (RCC) error occurs while attempting to access the GFCR in the #IBMMP4 record, general file restart copies the GFCR information from the GFCR in the #IBMM4 records to the #IBMMP4 record type.
  3. If a new processor is added to the loosely coupled complex with 32-way loosely coupled processor support, general file restart initializes the GFCR in the #IBMMP4 record type using premount information in segment CV2D.

The GFCR information in the #IBMM4 records is not changed.

General Data Set (GDS)

GDS support currently uses ordinal numbers from processor shared fixed record type #DSCRI for restart control records (RCRs). The logical ordinal number mapping for a processor is based on the assignment of every eighth ordinal because a maximum of eight processors are allowed. With 32-way loosely coupled processor support, the general data set RCRs are allocated to processor unique record type #DSCRU.

Migration to the #DSCRU processor unique record type occurs during GDS restart. Each processor migrates or initializes only its own records. GDS restart does the following:

  1. If the RCC has a value of X'FE', the RCRs are initialized in the #DSCRU records from the premount information in segments CVZE and CVZF.
  2. If the RCRs were not initialized from the premount information and the processor being IPLed is an existing processor, the #DSCRI records for that processor are copied to the #DSCRU records type.
  3. If the TPF 4.1 system is unable to read the RCR in the first #DSCRI record or if this is a new processor with 32-way loosely coupled processor support being added to the loosely coupled complex, the premount information in segments CVZE and CVZF is used to initialize the #DSCRU records.

The RCR information in the #DSCRI records is not changed.

Interprocessor Communications (IPC)

IPC uses an 8-bit mask to represent the processors in the loosely coupled complex. To support 32-way loosely coupled processors, IPC has been extended to use the list facility originally implemented for the internal event facility (IEF).

The list facility allows an IPC transmission to specify the following processor groupings as a destination:

Keypoint Accessing

32-way loosely coupled processor support for keypoint accessing addresses the following three areas:

Keypoint Ordinals
The keypoint ordinal table (CX0KPO) is expanded in place to support the additional processors. Equates CXPR0 - CXPR7 are removed, with equate SAMXPRO replacing the function of the CXPR7 equate.

Keypoint Status
The status table for keypoints loaded in the TPF 4.1 system is kept in the keypoint control records located in ordinal 0 of the #KBA and #KSA1 - #KSA8 records, and in #KPTCNTL (#IBMM4 ordinal 54). The status is indexed in the table by keypoint and processor.

To support 32-way loosely coupled processors using the same records, the table entry size has been reduced to 16 bytes and indexing into the table has been changed to use the keypoint ordinal in CX0KPO.

During coexistence, the record retriever function converts the status table to its new format when reading from file. When all processors are using 32-way loosely coupled processor support, use the ZMIGR command to convert the table to the new format on file. See TPF Operations for more information about the ZMIGR command.

#KEYPT
Because the location of keypoint fallback extents depends on the number of processors that are defined, there are problems with existing valid keypoint fallback extents when new processors are added to the TPF complex. Additionally, the records defined by #KEYPT to store the copies cannot be relocated because they may be followed by other record types that cannot be relocated.

To resolve these problems, keypoint fallback extents have been moved to their own record type, #KFBX0 - #KFBXnnn. To allow expansion as new processors are added to the TPF complex, a keypoint pointer record has been created in ordinal 0 for #KEYPT ordinals #KFBX0 - #KFBXnnn that allows the keypoint to be stored in multiple file extents (multiple RAMFIL statements along with the PRIOR parameter can be used to define these record types).

The new keypoint pointer record is created and updated during TPF 4.1 system restart. The ZKPTR command has been implemented so that you can control how system restart processes the keypoint pointer records if an error occurs. See TPF Operations for more information about the ZKPTR command.

Recoup

To save system resources and allow for future expansion, the #SONRPE records that were used for recoup chain chasing are being replaced with processor shared fixed file records #SONRPEx, where x is the ordinal number for the processor for which the record is used.

For a base-only system, the only record required is #SONRPE0. For a loosely coupled complex, each of the first eight processors requires a record. All processors after the first eight do not require a #SONRPEx record. For example, if there are eight processors, the #SONRPEx records that are used are shown in Table 1192.

Table 1192. #SONRPEx Records for an Eight-Processor Loosely Coupled Complex with 32-Way Loosely Coupled Processor Support

Processor ID Processor Ordinal #SONRPEx Used
B 0 #SONRPE0
C 1 #SONRPE1
D 2 #SONRPE2
E 3 #SONRPE3
F 4 #SONRPE4
G 5 #SONRPE5
Z 6 #SONRPE6
0 7 #SONRPE7

To handle the additional processors in a 32-way loosely coupled complex, the number of #FC33 fixed file records is increased from 65 to 257. The @@BUSED field, which contains bit maps used to track use of #FC33 records, has been replaced by the @@BUSED32 field, which supports 32 processors..

Operating Environment Requirements and Planning Information

There are none.

Interface Changes

The following section summarizes interface changes.

C/C++ Language

The following section summarizes C/C++ language changes. This information is presented in alphabetic order by the type of C/C++ language information. See the TPF C/C++ Language Support User's Guide and TPF Application Programming for more information about the C/C++ language.

Build Scripts

Table 1193 summarizes changes to the build scripts used by the build tool. This information is presented in alphabetic order by the name of the build script.

Table 1193. Changes to Build Scripts for 32-Way Loosely Coupled Processor Support

Build Script Type New, Changed, or No Longer Supported? Description of Change
CIKFBS DLM New Keypoint control record conversion utility for 32-way loosely coupled processor support.
CIKZBS DLM New Adds the KEYPOINT parameter to the ZMIGR command for 32-way loosely coupled processor support.
CVZ5BS DLM New Read and validate keypoint pointer record for 32-way loosely coupled processor support.
CVZ6BS DLM New System restart keypoint pointer record validation and update for 32-way loosely coupled processor support.
CVZ7BS DLM New Provides the ZKPTR command for 32-way loosely coupled processor support.
CVZ8BS DLM New Builds the keypoint pointer record extent table for 32-way loosely coupled processor support.

Dynamic Load Module (DLM) Stubs

Table 1194 summarizes changes to the dynamic load module (DLM) stubs. This information is presented in alphabetic order by the name of the DLM stub. See TPF Application Programming for more information about the DLM stubs.

Table 1194. Changes to Dynamic Load Module (DLM) Stubs for 32-Way Loosely Coupled Processor Support

Name of DLM Stub New or No Longer Supported?
CIKF New
CVZ4 New
CVZ5 New
CVZ8 New

General Use C/C++ Language Header Files

Table 1195 summarizes the general use C/C++ language header file changes. This information is presented in alphabetic order by the name of the general use C/C++ language header file.

General use means these header files are available for your use.

Table 1195. Changes to General Use C/C++ Language Header Files for 32-Way Loosely Coupled Processor Support

C/C++ Language Header File New, Changed, or No Longer Supported? Do You Need to Recompile Segments? Segments to Recompile
c$cflv.h Not Changed Yes User-defined segments that reference c$cflv.h.
c$cx0ck.h Changed Yes Programs included in Table 1208.
c$fbd0.h Changed Yes FTBD00, FTPS03, FTVA01.
c$fer0.h Changed No Not Applicable.
c$fva0.h Changed Yes Programs included in Table 1208.
c$ic0ck.h Changed Yes User-defined segments only.
c$idskpt.h Changed Yes Programs included in Table 1208.
c$pi1dt.h Changed Yes User-defined segments only.
c$si3ct.h Changed Yes User-defined segments that reference SI3DEST and programs included in Table 1208.
c$syseq.h Changed Yes Programs included in Table 1208.
c$tglb.h Changed Yes User-defined segments that reference c$tglb.h, segments in Table 1208, and CFL5, CFL6, CFL7, CFLE, CLM8LK. Link-edit DLMs CFL5, CFL6, CFLE, and CLM8.
c$vfac.h Not Changed Yes User-defined segments that reference c$vfac.h.
sysapi.h Changed Yes User-defined segments only.
tpfapi.h Changed Yes User-defined segments only.

Implementation-Specific C/C++ Language Header Files (IBM Use Only)

Table 1196 summarizes the general use C/C++ language header file changes that are for IBM use only. This information is presented in alphabetic order by the name of the general use C/C++ language header file.

Table 1196. Changes to Implementation-Specific C/C++ Language Header Files (IBM Use Only) for 32-Way Loosely Coupled Processor Support

C/C++ Language Header File (IBM Use Only) New, Changed, or No Longer Supported? Do You Need to Recompile Segments? Segments to Recompile
i$dlok.h Changed No Not Applicable
i$kptr.h New No Not Applicable.
i$mqrt.h Changed Yes CMQCKP, CMQGRU, CMQRCV, CMQMRM, CMQXRM.
i$netd.h Changed Yes CINET1, CINET3, CINET4, CINET5, CINET6, CINET7, CINET8, CINETA, CINETN, and programs included in Table 1208.
i$tmcr.h Changed Yes CL15, CXPRCV, CXQRCV.
zimag.h Changed Yes Programs included in Table 1208.
zimageq.h Changed Yes Programs included in Table 1208.
zimagmsg.h Changed Yes CIMO, CIMP, CIMQ, CIMU and programs included in Table 1208.
ztpld.h Changed Yes CIL0, CIL1, CIL2, CIL3, CIL4, CIL5, CIL6, CIL7, CILA, CILB, CILD, CILF, CILO, CILX.

Library Interface Scripts

There are no changes.

Link-Edited Modules

Table 1197 summarizes changes to the link-edited modules shipped by IBM, which should go into a data set with attributes DCB=(RECFM=U,LRECL=80,BLKSIZE=1200). This information is presented in alphabetic order by the name of the link-edited module.

Table 1197. Changes to Link-Edited Modules for 32-Way Loosely Coupled Processor Support

Link-Edited Module New, Changed, or No Longer Supported? Description of Change
CDCP Not Changed References equate macro file TPFGLB.
CDNF Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CFL5 Not Changed References C header file c$tglb.h.
CFL6 Not Changed References C header file c$tglb.h.
CFLE Not Changed References C header file c$tglb.h.
CFLK Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CIKB Not Changed Changes to ZIMAG command for 32-way loosely coupled processor support.
CIKF New Keypoint control record conversion utility for 32-way loosely coupled processor support.
CIKZ New Adds the KEYPOINT parameter to the ZMIGR command for 32-way loosely coupled processor support.
CILA Not Changed Updates to members for 32-way loosely coupled processor support.
CILB Not Changed Updates to members for 32-way loosely coupled processor support.
CILO Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CIMA Not Changed Updates to members for 32-way loosely coupled processor support.
CIMN Not Changed Updates to members for 32-way loosely coupled processor support.
CIMU Not Changed Updates to members for 32-way loosely coupled processor support.
CL15 Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CL40 Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CL4B Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CLM8 Not Changed References C header file c$tglb.h.
CLTW Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CLTX Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CLTZ Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CMQM Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CMQX Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CRPC Not Changed Members recompiled because of updates for 32-way loosely coupled processor support.
CTFT Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CTUU Not Changed Members CTU1, CTU2, and CTU4 changed for 32-way loosely coupled processor support.
CTXO Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CUIU Not Changed Members need to be recompiled because of updates for 32-way loosely coupled processor support.
CVZ5 New Reads and validates keypoint pointer record for 32-way loosely coupled processor support.
CVZ6 New System restart validate and update keypoint pointer record for 32-way loosely coupled processor support.
CVZ7 New Adds the ZKPTR command for 32-way loosely coupled processor support.
CVZ8 New Builds the keypoint pointer record extent table for 32-way loosely coupled processor support.

Members

Table 1198 summarizes changes to members. This information is presented in alphabetic order by the name of the member.

Notes:

  1. You must recompile or reassemble a member if it has changed.

  2. You must prelink and link a dynamic load module (DLM) if it has changed.

Table 1198. Changes to Members for 32-Way Loosely Coupled Processor Support

Member DLM/DLL/LLM Name Type New, Changed, or No Longer Supported? Member Type Description of Change
CCOMIC CTAL LLM Changed C Language Use new commit and rollback control table pointer for 32-way loosely coupled processor support.
CDNSSC CDNC DLM Changed C Language Updated IPC base support and user level for 32-way loosely coupled processor support.
CEL5 CEL5 DLM Changed C Language Updated for PIDT mask usage changes.
CFDSC CFLY DLM Changed C Language Updated for PIDT mask usage changes.
CFLW CFLK DLM Changed Assembler Updated IPC base support and user level for 32-way loosely coupled processor support.
CGENLC CTAL LLM Changed Assembler Changes to the tpf_genlc function.
CIKA CIMA DLM Changed C Language Make keypoint control items keypoint ordinal indexed and split #KEYPT support between #KEYPT and #KFBXn fixed file records.
CIKB CIKB DLM Changed C Language Split #KEYPT support between #KEYPT and #KFBXn fixed file records.
CIKF CIKF DLM New C Language Keypoint control record conversion utility for 32-way loosely coupled processor support.
CIKZ CIKZ DLM New C Language Added support for the KEYPOINT parameter of the ZMIGR command.
CIL0 CILA DLM Changed C Language Use the SAMXPRO equate value for the maximum number of processors and make keypoint control items keypoint ordinal indexed.
CIL5 CILA DLM Changed C Language Make keypoint control items keypoint ordinal indexed; and convert keypoint control record to 32-way loosely coupled format when read, and back to the previous format when filed.
CILB CILB DLM Changed C Language Make keypoint control items keypoint ordinal indexed and add a new message.
CIMN CIMN DLM Changed C Language Convert keypoint control record to 32-way loosely coupled format when read, and back to the previous format when filed.
CIMO CIMA DLM Changed C Language Use the SAMXPRO equate value for the maximum number of processors, and split #KEYPT support between #KEYPT and #KFBXn fixed file records.
CIMQ CIMA DLM Changed C Language Use the SAMXPRO equate value for the maximum number of processors, and split #KEYPT support between #KEYPT and #KFBXn fixed file records.
CIMT CIMA DLM Changed C Language Use the SAMXPRO equate value for the maximum number of processors, make keypoint control items keypoint ordinal indexed, and split #KEYPT support between #KEYPT and #KFBXn fixed file records.
CINET2 CDNS, CLTV, CLTY, CMAT DLM Changed C Language New Internet daemon (INETD) record type.
CL12 CL12 DLM Changed C Language Use new commit and rollback control table pointer for 32-way loosely coupled processor support.
CL13 CL13 DLM Changed C Language Use new commit and rollback control table pointer for 32-way loosely coupled processor support.
CL14 CL14 DLM Changed C Language Use new commit and rollback control table pointer for 32-way loosely coupled processor support.
CL16 CL16 DLM Changed C Language Use new commit and rollback control table pointer for 32-way loosely coupled processor support.
CL40 CL40 DLM Changed C Language Removed check on HALF_MEG for base only path.
CL42 CL42 DLM Changed C Language Use new commit and rollback control table pointer for 32-way loosely coupled processor support.
CL4A CL40 DLM Changed C Language Added merged file address table full to deadlock detection and replaced hardcoded '8' processors with TPFGLB equate SAMXPRO.
CL4B CL4B DLM Changed C Language Replace hardcoded '8' processors with TPFGLB equate SAMXPRO.
CL4D CL40 DLM Changed C Language Added merged file address table full to deadlock detection.
CLCC CLCC DLM Changed C Language New Common Link Access to Workstation (CLAW) record type.
CLCD CLCD DLM Changed C Language New CLAW record type.
CLTR CLTR DLM Changed C Language New CLAW record type.
CLTU CLTN DLM Changed C Language New CLAW record type.
CMQRM CMQS DLL Changed C++ Language Use new commit and rollback control table pointer for 32-way loosely coupled processor support.
CSIPCC CTAL LLM Changed Assembler Updated to support 32-way loosely coupled processors.
CTU1 CTUU DLM Changed C Language Updated for 32-way loosely coupled processor support.
CTU2 CTUU DLM Changed C Language Updated for 32-way loosely coupled processor support.
CTU4 CTUU DLM Changed C Language Updated for 32-way loosely coupled processor support.
CVZ5 CVZ5 DLM New C Language Read and validate keypoint pointer record.
CVZ6 CVZ6 DLM New C Language Validate and update keypoint pointer record during system restart.
CVZ7 CVZ7 DLM New C Language Adds support for the ZKPTR command.
CVZ8 CVZ8 DLM New C Language Builds the keypoint pointer record extent table.
CVZ9 CVZ8 DLM New Assembler Gets DASD constants for the keypoint record build extent table function.
CXACMT CTAL LLM Changed Assembler Updated to point to 32-way loosely coupled processor table.
CXAEND CTAL LLM Changed Assembler Updated to point to 32-way loosely coupled processor table.
CXAPRP CTAL LLM Changed Assembler Updated to point to 32-way loosely coupled processor table.
CXARCV CTAL LLM Changed C Language Use new commit and rollback control table pointer for 32-way loosely coupled processor support.
CXARLB CTAL LLM Changed Assembler Updated to point to 32-way loosely coupled processor table.
CXASTR CTAL LLM Changed Assembler Updated to point to 32-way loosely coupled processor table.
CXPCMT CTAL LLM Changed Assembler Updated to point to 32-way loosely coupled processor table.
CXPRLB CTAL LLM Changed Assembler Updated to point to 32-way loosely coupled processor table.
CXQCMT CTAL LLM Changed Assembler Updated to point to 32-way loosely coupled processor table.
CXQPRP CTAL LLM Changed Assembler Updated to point to 32-way loosely coupled processor table.
CXQRLB CTAL LLM Changed Assembler Updated to point to 32-way loosely coupled processor table.

Object Code Only (OCO) Stubs

There are no changes.

Configuration Constant (CONKC) Tags

There are no changes.

l

Control Program Interface (CINFC) Tags

There are no changes.

Copy Members

Table 1199 summarizes the copy member changes. This information is presented in alphabetic order by the name of the copy member.

Table 1199. Changes to Copy Members for 32-Way Loosely Coupled Processor Support

Copy Member Type New, Changed, or No Longer Supported Segment Where Copy Member is Included Name of Link-Edited Module DLM, DLL, LLM, or Control Program Description of Change
CDC1 CP Changed CCDCOL CPS0 Control Program Updated for changes to the SIPCC macro interface.
CICR CP Changed CCNUCL CPS0 Control Program Changes to comments only.
CICS CP Changed CCNUCL CPS0 Control Program Updated for 32-way loosely coupled processor support.
CIEF CP Changed CCCIEF CPS0 Control Program Changes to the GENLC macro.
CJ341 Real-Time Assembler Changed CJ005 CJ00 LLM Changes to interprocessor communications (IPC) user level.
CL10 CP Changed CCTLOG CPS0 Control Program Use new commit and rollback control table pointer for 32-way loosely coupled processor support.
CL20 CP Changed CCTLOG CPS0 Control Program Use new commit and rollback control table pointer for 32-way loosely coupled processor support.
CL30 CP Changed CCTLOG CPS0 Control Program Use new commit and rollback control table pointer for 32-way loosely coupled processor support.
CNOM CP Changed CCSICF CPS0 Control Program Changes to the SIPCC macro.
CNP0 CP Changed CCSICF CPS0 Control Program Changes to the SIPCC macro.
CNP6 CP Changed CCSICF CPS0 Control Program Changes to the SIPCC macro.
CT09 CP Changed CCCTIN CPS0 Control Program Added support for #RLOG9 - 32.
CT41 CP Changed CCCTIN CPS0 Control Program Split #KEYPT support between #KEYPT and #KFBXn fixed file records.
IB01 Real-Time Assembler Changed IPLB Not Applicable Not Applicable Split #KEYPT support between #KEYPT and #KFBXn fixed file records, and added new fallback extent support.
IB02 Real-Time Assembler Changed IPLB Not Applicable Not Applicable Split #KEYPT support between #KEYPT and #KFBXn fixed file records, added new fallback extent support, and updated for CTKC coexistence.
IB03 Real-Time Assembler Changed IPLB Not Applicable Not Applicable Split #KEYPT support between #KEYPT and #KFBXn fixed file records, and added new fallback extent support.
IB07 Real-Time Assembler Changed IPLB Not Applicable Not Applicable Updated for CTKI coexistence.
IBF1 Real-Time Assembler Changed IPLB Not Applicable Not Applicable Split #KEYPT support between #KEYPT and #KFBXn fixed file records, and added new fallback extent support.
IBF2 Real-Time Assembler Changed IPLB Not Applicable Not Applicable Updated for PIDT mask usage.

Fixed File Records

Table 1200 summarizes fixed file record changes. This information is presented in alphabetic order by the name of the fixed file record.

Table 1200. Changes to Fixed File Records for 32-Way Loosely Coupled Processor Support

Fixed File Record New, Changed, or No Longer Supported? Description of Change
#BRIDCOR Changed Increased required minimum number of ordinals to 256.
#CB8HD No Longer Supported Replaced by fixed file record #HDREC.
#CN1ST New Expanded subsystem state table (CN1ST) to support 32-way loosely coupled processors.
#DSCRI No Longer Supported Replaced by #DSCRU to support 32-way loosely coupled processors.
#DSCRU New General data set (GDS) support, replacing #DSCRI.
#HDREC New New record to expand multi-processor interconnect facility (MPIF) hardware definition to support 32-way loosely coupled processors.
#IBMMP4 Changed Increased the required minimum number of ordinals to 100.
#IBMMS Changed Increased the minimum number of ordinals to 60.
#IDCF1 New New record to expand Internet daemon configuration file (IDCF) to support 32-way loosely coupled processors.
#KBA Changed Reduced minimum number of ordinals to (number_of_processor-unique_keypoints × number_of_processors) + number_of_processor-shared keypoints + 1.
#KEYPT Changed Changed to allow multiple keypoint fallback extents (more than one on RAMFIL statement).
#KFBX0 - 254 New New records to support keypoint fallback extents for 32 loosely coupled processors.
#KSA1 - #KSA8 Changed Reduced minimum number of ordinals to (number_of_processor-unique_keypoints × number_of_processors) + number_of_processor-shared keypoints + 1.
#PDREC Changed Reduced minimum number of ordinals to 4.
#PDREU New New record to expand MPIF path definition to support 32-way loosely coupled processors.
#RC8RFS Changed Increased the minimum number of ordinals from 65 to 257.
#RLOG9 - #RLOG32 New New commit and rollback logging records for processors 9 - 32.
#SONRPE No Longer Supported Replaced by #SONRPE0 - 7 to support 32-way loosely coupled processors.
#SONRPE0 - 7 New New recoup pseudo directories for processors 0 - 7.

Macros

The following section summarizes the macro changes. This information is presented in alphabetic order by the type of macro.

Advanced Program-to-Program Communications (APPC) Macros

There are no changes.

Communication Macros and Statements

There are no changes.

Data Macros

Table 1201 summarizes the data macro changes. This information is presented in alphabetic order by the name of the data macro.

Table 1201. Changes to Data Macros for 32-Way Loosely Coupled Processor Support

Data Macro New, Changed, or No Longer Supported? Do You Need to Reassemble Programs Using This Data Macro? Programs to Reassemble
BRPEQ Changed Yes Programs included in Table 1208.
CB8HD Changed Yes Programs included in Table 1208.
CB9PD Changed Yes Programs included in Table 1208.
CK8KE Changed Yes CCNUCL, CCCCP1, CCCTIN, CGT0, CGT1, CIJG, CVAD, CVAU, CVFF, CVFO, CVFP, CVFQ, CVHA, CVHB, CVHC, CVHF, CVHL, CVHY, CVIQ, CVKM, CVKN, CVLA, CVPX, CVP1, CVRN, CWA0, CWBL, CWGM, CWGO, CWGX, CYYE, XLAA, XLDD, XLEF, XLJK.
CN1ST Changed Yes Programs included in Table 1199 and user-defined.
CONKC Changed Yes CONK
CR0AT Changed Yes CCCCP1, CCCCP4, CCCTIN, CCNUCL, CGT0, CGT1, CGT2, CGT4, CGT5, CGT8, CGT9, CIJG, CMID, COUF, CSOR, CTKT, CVPX, CVAD, CVAU, CVFF, CVFO, CVFP, CVFQ, CVHA, CVHB, CVHC, CVHF, CVHL, CVHY, CVIQ, CVKM, CVKN, CVLA, CVP1, CVRN, CWA0, CWBL, CWGM, CWGO, CWGX, CYYE, IPLB, XLAA, XLDD, XLEF, XLJK.
CX0CK Changed Yes Programs included in Table 1208.
DCTIGT Changed No Not Applicable
DCTMGT Changed Yes Programs included in Table 1208.
GENFD Changed Yes Programs included in Table 1208.
GO1GO Changed Yes BAM1, GLBL, GOG1, GOG3, GOG5, GOGO.
I80I8 Changed Yes Programs included in Table 1208.
I82I8 Changed Yes Programs included in Table 1208.
IB0CT Changed Yes Programs included in Table 1199 and in Table 1208.
IC0CK Changed Yes Programs included in Table 1199 and user-defined.
ICFLV Not Changed Yes User-defined programs that reference data macro ICFLV.
ICRCT Changed Yes CCTLOG, CDCR, CL26, CL99, CLH0, CLH2, CTMCCR, CTMPRP, CXACMT, CXAEND, CXAPRP, CXARLB, CXASTR, CXPCMT, CXPRCV, CXPRLB, CXQCMT, CXQPRP, CXQRCV, CXQRLB, IPLB, JCD4, JCS0.
IDSDLR Changed Yes Programs included in Table 1208.
IDSKPT Changed No Not Applicable.
IDSSST Changed No Not Applicable.
IKPTR New No Not Applicable.
LDCRL Changed Yes ACPL and ALDR
NC0CB Changed Yes Programs included in Table 1208.
PI1DT Changed Yes Programs included in Table 1199 and user-defined.
RC1IT Changed Yes CONN
RECOUP Changed Yes Programs included in Table 1199 and user-defined.
SI3CT Changed Yes Programs included in Table 1199 and user-defined.
SI4CT Changed No Not Applicable.
ST0TB Changed Yes OSTGIP, OSTGOT, OSTGP2, OSTGRT, OSTGUP.
VF0AC Not Changed Yes User-defined programs that reference data macro VF0AC.

General Macros

Table 1202 summarizes the general macro changes. This information is presented in alphabetic order by the name of the general macro. See TPF General Macros for a complete description of all general macros.

Table 1202. Changes to General Macros for 32-Way Loosely Coupled Processor Support

General Macro New, Changed, or No Longer Supported? Do You Need to Reassemble Programs? Programs to Reassemble
GENLC Changed No Not Applicable.

Selected Equate Macros

Table 1203 summarizes the selected equate macro changes. This information is presented in alphabetic order by the name of the selected equate macro.

Table 1203. Changes to Selected Equate Macros for 32-Way Loosely Coupled Processor Support

Selected Equate Macro New, Changed, or No Longer Supported? Do You Need to Reassemble Programs? Programs to Reassemble
CFMDC Changed Yes ICDF, STPP.
CPSEQ Changed No Not Applicable.
CZ1SE Changed No Not Applicable.
CZ3CP Changed No Not Applicable.
SYSEQ Changed No Not Applicable.
TPFGLB Changed Yes User-defined programs that use TPFGLB or data macros ICFLV or VF0AC, programs included in Table 1208, and B0SH, BOFH, BRSH, BXAT, CCCTIN, CCDBAF, CCFADC, CCNUCL, CCRCSC, CCSONS, CCTLOG, CCVAGE, CCVFAC, CDCR, CLMK, CLML, CLMN, CORB, CPAA, CTKR, CTKT, CVF2, CVF4, CVF7, CVF8, CVF9, CVFS, CVFX, CZXM, IPLB, JCF0, JCS0. Link-edit DLM CDCP.

Structured Programming Macros (SPMs)

There are no changes.

System Initialization Program (SIP) Skeleton and Internal Macros (Inner Macros)

Table 1204 summarizes the system initialization program (SIP) skeleton and internal macro changes. This information is presented in alphabetic order by the name of the SIP skeleton and internal macro. If the SIP skeleton and internal macro (inner macro) is changed, you must reassemble the SIP Stage I deck and run the appropriate job control language (JCL) jobs from the SIP Stage II deck.

Table 1204. Changes to SIP Skeleton and Internal Macros for 32-Way Loosely Coupled Processor Support

SIP Skeleton and Internal Macro New, Changed, or No Longer Supported?
GENC Changed
GEND Changed
GENR Changed
SKANTD Changed
SKCTKC Changed
SKCTKI Changed
SKCTKX Changed
SKGLB Changed
SKRCIT Changed
SKSET Changed
SPERR Changed
SPERRG Changed

System Initialization Program (SIP) Stage I Macros and Statements

Table 1205 summarizes system initialization program (SIP) Stage I macro and statement changes. This information is presented in alphabetic order by the name of the SIP Stage I macro. See TPF System Generation for a complete description of the SIP Stage I macros. If the SIP Stage I macro is changed, you must run the appropriate job control language (JCL) jobs from the SIP Stage II deck

See System Initialization Program (SIP) and System Generation Changes for a description of other system generation changes you must make.

Table 1205. Changes to SIP Stage I Macros and Statements for 32-Way Loosely Coupled Processor Support

SIP Stage I Macro New, Changed, or No Longer Supported?
CONFIG Changed
CRASTB Changed
GENSIP Changed
RAM Changed
SPCPU Changed
SPGLB Changed
SPPGML Changed
SPREPT Changed

System Initialization Program (SIP) Stage II Macros

Table 1206 summarizes system initialization program (SIP) Stage II macro changes. This information is presented in alphabetic order by the name of the SIP Stage II macro. If IBMPAL is changed, you must run the system allocator (SALO) and load the new program allocation table (PAT) to the TPF 4.1 system.

Table 1206. Changes to SIP Stage II Macros for 32-Way Loosely Coupled Processor Support

SIP Stage II Macro New, Changed, or No Longer Supported?
IBMPAL Changed

System Communication Keypoint (SCK) Generation Macros

There are no changes.

System Macros

Table 1207 summarizes system macro changes. This information is presented in alphabetic order by the name of the system macro. See TPF System Macros for a complete description of all system macros.

Table 1207. Changes to System Macros for 32-Way Loosely Coupled Processor Support

System Macro New, Changed, or No Longer Supported? Do You Need to Reassemble Programs? Programs to Reassemble
SIPCC Changed Yes User-defined programs only.

System Macros (IBM Use Only)

There are no changes.

Segments

Table 1208 summarizes segment changes. This information is presented in alphabetic order by the name of the segment.

Table 1208. Changes to Segments for 32-Way Loosely Coupled Processor Support

Segment Type Link-Edit Module (Where Offline Segment Is Linked) New, Changed, or No Longer Supported? Description of Change
ACPL Offline Assembler Not Applicable Changed Make keypoint control items keypoint ordinal indexed; and convert keypoint control records to 32-way loosely coupled format when read, and back to the previous format when filed. Split #KEYPT support between #KEYPT and #KFBXn fixed file records.
B0BK Real-Time Assembler Not Applicable Changed Updated for the SIPCC macro list interface.
B0P0 Real-Time Assembler Not Applicable Changed Added restriction on Recoup and updated for changes to SIPCC macro interface.
B0P3 Real-Time Assembler Not Applicable Changed Updated for the SIPCC macro list interface.
B0P5 Real-Time Assembler Not Applicable Changed Updated for the SIPCC macro list interface.
B0PE Real-Time Assembler Not Applicable Changed Updated for the SIPCC macro list interface.
B1A0 Real-Time Assembler Not Applicable Changed Updated for changes to the @@BUSED field in the RECOUP DSECT and changes to SIPCC macro interface.
B1A4 Real-Time Assembler Not Applicable Changed Updated for changes to the @@BUSED field in the RECOUP DSECT.
B1BK Real-Time Assembler Not Applicable Changed Updated for the SIPCC macro list interface.
BAM0 Real-Time Assembler Not Applicable Changed Updated maximum processor value.
BAM1 Real-Time Assembler Not Applicable Changed Updated for 32-way loosely coupled globals format.
BCPE Real-Time Assembler Not Applicable Changed Updated for changes to the @@BUSED field in the RECOUP DSECT.
BCPU Real-Time Assembler Not Applicable Changed Updated for changes to the 1052 FC33 record.
BCPY Real-Time Assembler Not Applicable Changed Updated for changes to the #SONRPEx fixed file records.
BCPZ Real-Time Assembler Not Applicable Changed Updated for changes to the #SONRPEx fixed file records.
BDBA Real-Time Assembler Not Applicable Changed Updated for changes to PIDT mask usage.
BKA0 Real-Time Assembler Not Applicable Changed Updated maximum processor value.
BKP0 Real-Time Assembler Not Applicable Changed Updated for the SIPCC macro list interface.
BKP3 Real-Time Assembler Not Applicable Changed Updated for the SIPCC macro list interface.
BKP4 Real-Time Assembler Not Applicable Changed Updated for the SIPCC macro list interface.
BKP5 Real-Time Assembler Not Applicable Changed Updated for the SIPCC macro list interface.
BKPA Real-Time Assembler Not Applicable Changed Updated recoup duplicate message sender for 32-way loosely coupled processor support.
BLOG Real-Time Assembler Not Applicable Changed Updated for changes to the following:
  • @@BUSED field in the RECOUP DSECT
  • 1052 FC33 record.
BLOH Real-Time Assembler Not Applicable Changed Updated for changes to the @@BUSED field in the RECOUP DSECT.
BOF0 Real-Time Assembler Not Applicable Changed Updated for changes to the CPU ID in the I82I8 data macro.
BOF3 Real-Time Assembler Not Applicable Changed Updated for changes to #SONRPEx fixed file records.
BOF4 Real-Time Assembler Not Applicable Changed Updated for changes to #SONRPEx fixed file records.
BOF7 Real-Time Assembler Not Applicable Changed Updated for 1052 I8 record.
BOF8 Real-Time Assembler Not Applicable Changed Updated for changes to the CPU ID in the I82I8 data macro.
BOFA Real-Time Assembler Not Applicable Changed Updated for the following changes:
  • Interprocessor communications (IPC) base support and user level
  • @@BUSED field in the RECOUP DSECT
  • 1052 FC33 record
  • I82I8 data macro CPU ID.
BOFF Real-Time Assembler Not Applicable Changed Updated for changes to the #SONRPEx fixed records.
BPDH Real-Time Assembler Not Applicable Changed Updated for changes to the #SONRPEx fixed records.
BRCP Real-Time Assembler Not Applicable Changed Updated for the SIPCC macro list interface.
BRCQ Real-Time Assembler Not Applicable Changed Updated for changes to the 1052 FC33 record.
BRID Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
BRPE Real-Time Assembler Not Applicable Changed Updated for changes to the @@BUSED field in the RECOUP DSECT.
BRV0 Real-Time Assembler Not Applicable Changed Updated for changes to the #SONRPEx fixed records.
BRV1 Real-Time Assembler Not Applicable Changed Updated for changes to the #SONRPEx fixed records.
BRV2 Real-Time Assembler Not Applicable Changed Updated for changes to the #SONRPEx fixed records.
BRV3 Real-Time Assembler Not Applicable Changed Updated for changes to the #SONRPEx fixed records.
BRV5 Real-Time Assembler Not Applicable Changed Updated for changes to the #SONRPEx fixed records.
BRVT Real-Time Assembler Not Applicable New Added recoup function to the ZMIGR command.
BRYO Real-Time Assembler Not Applicable Changed Updated for changes to the @@BUSED field in the RECOUP DSECT.
BRYU Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
BWRT Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
BXA1 Real-Time Assembler Not Applicable Changed Updated for changes to PIDT mask usage, changes to the SIPCC macro interface, and changes to #KEYPT and #KFBXn fixed file records.
BXA2 Real-Time Assembler Not Applicable Changed Updated to use CYYF to retrieve #CN1ST fixed record type.
BXAB Real-Time Assembler Not Applicable Changed Updated to use 32-way loosely coupled processor support.
BXBL Real-Time Assembler Not Applicable Changed Split #KEYPT support between #KEYPT and #KFBXn fixed file records.
BXDP Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
BXPC Real-Time Assembler Not Applicable Changed Updated for 32-way loosely coupled processor support.
BXPR Real-Time Assembler Not Applicable Changed Updated for 32-way loosely coupled processor support.
C277 Real-Time Assembler Not Applicable Changed Target TPF-C no longer supported for SIPCC.
CBE2 Real-Time Assembler Not Applicable Changed Updated MPIF help message.
CBG2 Real-Time Assembler Not Applicable Changed New MPIF record types or expanded data structures.
CBO0 Real-Time Assembler Not Applicable Changed New MPIF record types or expanded data structures.
CBO1 Real-Time Assembler Not Applicable Changed New MPIF record types or expanded data structures.
CBP0 Real-Time Assembler Not Applicable Changed New MPIF record types or expanded data structures.
CBP1 Real-Time Assembler Not Applicable Changed New MPIF record types or expanded data structures.
CBP3 Real-Time Assembler Not Applicable Changed New MPIF record types or expanded data structures.
CBR0 Real-Time Assembler Not Applicable Changed New MPIF record types or expanded data structures.
CBR1 Real-Time Assembler Not Applicable Changed New MPIF record types or expanded data structures.
CBR2 Real-Time Assembler Not Applicable Changed New MPIF record types or expanded data structures.
CBY0 Real-Time Assembler Not Applicable Changed New MPIF record types or expanded data structures.
CDL0 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors.
CDL1 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors and changes to the SIPCC macro interface.
CDL2 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors and changes to the SIPCC macro interface.
CDL3 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors and changes to the SIPCC macro interface.
CDL5 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks and modified communications to support 32-way loosely coupled processors.
CDL6 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks and modified communications to support 32-way loosely coupled processors.
CDL8 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors.
CFL8 Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CFL9 Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CHEA Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors.
CHKB Real-Time Assembler Not Applicable Changed Comments were updated for 32-way loosely coupled processors.
CHKR Real-Time Assembler Not Applicable Changed Comments were updated for 32-way loosely coupled processors.
CHZS Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors.
CJ05 Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CL11 Real-Time Assembler Not Applicable Changed Changed to use new commit and rollback pointer for 32-way loosely coupled processor support expanded table and expanded table of system log record FACE-type equates.
CL21 Real-Time Assembler Not Applicable Changed Changed to use new commit and rollback pointer for 32-way loosely coupled processor support expanded table and expanded table of system log record FACE-type equates.
CL22 Real-Time Assembler Not Applicable Changed Expanded table of system log record FACE-type equates for 32-way loosely coupled processors.
CL23 Real-Time Assembler Not Applicable Changed Changed to use new commit and rollback pointer for 32-way loosely coupled processor support expanded table and expanded table of system log record FACE-type equates.
CL24 Real-Time Assembler Not Applicable Changed Changed to use new commit and rollback pointer for 32-way loosely coupled processor support expanded table and expanded table of system log record FACE-type equates.
CL31 Real-Time Assembler Not Applicable Changed Changed to use new commit and rollback pointer for 32-way loosely coupled processor support expanded table.
CLM0 Real-Time Assembler Not Applicable Changed Changed to use new commit and rollback pointer for 32-way loosely coupled processor support expanded table.
CLM1 Real-Time Assembler Not Applicable Changed Updated for changes to PIDT mask usage.
CLME Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CLMF Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CLMG Real-Time Assembler Not Applicable Changed Updated for changes to PIDT mask usage.
CLMH Real-Time Assembler Not Applicable Changed Updated for changes to PIDT mask usage.
CLMI Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CLMM Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support and deleted unused save areas.
CLMO Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CLMP Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CLMR Real-Time Assembler Not Applicable Changed Updated for changes to PIDT mask usage.
CLMU Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CMT9 Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CMTQ Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CMVS Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CNAC Real-Time Assembler Not Applicable Changed Updated IPC base support and user level to decrement the active processor count and reset the 32-way loosely coupled processor support flag in PIDT when a processor is deactivated.
CNAE Real-Time Assembler Not Applicable Changed Added calls to CYYF to access the #CN1ST fixed file record type and updated IPC base support and user level for 32-way loosely coupled processor support.
CNAF Real-Time Assembler Not Applicable Changed Added calls to CYYF to access the #CN1ST fixed record type.
CNAH Real-Time Assembler Not Applicable Changed Added calls to CYYF to access the #CN1ST fixed record type and updated for changes to the SIPCC macro interface.
CNAI Real-Time Assembler Not Applicable Changed Updated to save and restore the registers of the calling routine.
CNAJ Real-Time Assembler Not Applicable Changed Added calls to CYYF to access the #CN1ST fixed record type and updated for changes to the SIPCC macro interface.
CNAK Real-Time Assembler Not Applicable Changed Updated comments and changes to the SIPCC macro interface.
CNBA Real-Time Assembler Not Applicable Changed Updated to support CTKI coexistence for 32-way loosely coupled processor support.
CNON Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CNOP Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CNOQ Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CNOR Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CNPH Real-Time Assembler Not Applicable Changed Added restriction on PROT.
CNPU Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
CNPY Real-Time Assembler Not Applicable Changed Updated CTKI and PIDT initialization and added calls to CYYF to access the #CN1ST fixed record type.
COAD Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
COAH Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CONN Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors.
COTB Real-Time Assembler Not Applicable Changed Updated for changes to PIDT mask usage.
CPAB Real-Time Assembler Not Applicable Changed Removed 8-way processor constraint in RCS support.
CPAI Real-Time Assembler Not Applicable Changed Removed 8-way processor constraint in RCS support.
CQAE Real-Time Assembler Not Applicable Changed Updated clock support for 32-way loosely coupled processors.
CQAL Real-Time Assembler Not Applicable Changed Updated clock support for 32-way loosely coupled processors.
CQAP Real-Time Assembler Not Applicable Changed Updated clock support for 32-way loosely coupled processors.
CQAQ Real-Time Assembler Not Applicable Changed Updated clock support for 32-way loosely coupled processors.
CSA0 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors.
CSA1 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors.
CSA2 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks and modified communications to support 32-way loosely coupled processors.
CSA8 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors.
CSAG Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors and for changes to the SIPCC macro interface.
CSAI Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
CSBS Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CSCD Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors.
CSCZ Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors.
CSG0 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors.
CSG9 Real-Time Assembler Not Applicable Changed Expanded 1-byte processor masks to support 32-way loosely coupled processors.
CSS1 Real-Time Assembler Not Applicable Changed Removed 8-way processor constraint in RCS support.
CSS8 Real-Time Assembler Not Applicable Changed Updated to add support for the RCS and IPC.
CTKS Real-Time Assembler Not Applicable Changed Updated for changes to PIDT mask usage, and split #KEYPT support between #KEYPT and #KFBXn fixed file records.
CVAB Real-Time Assembler Not Applicable Changed Added support for the ZMIGR and ZKPTR commands.
CVAQ Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CVGA Real-Time Assembler Not Applicable Changed Changed for general data set (GDS) restart control record structure in fixed record type #DSCRU.
CVGH Real-Time Assembler Not Applicable Changed Changed for GDS restart control record structure in fixed record type #DSCRU.
CVGP Real-Time Assembler Not Applicable Changed Changed for general file (GF) control record structure in fixed record type #IBMMP4.
CVGR Real-Time Assembler Not Applicable Changed Changed for GDS restart control record structure in fixed record type #DSCRU.
CVHF Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
CVPQ Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
CVPR Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CVPX Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
CVRM Real-Time Assembler Not Applicable Changed Updated for changes to PIDT mask usage.
CVRN Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
CVRQ Real-Time Assembler Not Applicable Changed Split #KEYPT support between #KEYPT and #KFBXn fixed file records, and added multiple fallback extent support.
CVUB Real-Time Assembler Not Applicable Changed Added GF control record migration status messages.
CVZ1 Real-Time Assembler Not Applicable Changed Updated for changes to PIDT mask usage, and new fallback extent record type support.
CVZ2 Real-Time Assembler Not Applicable Changed Split #KEYPT support between #KEYPT and #KFBXn fixed file records, and added multiple fallback extent support.
CVZ4 Real-Time Assembler Not Applicable New Provided support to split #KEYPT support between #KEYPT and #KFBXn fixed file records and map keypoint ordinal to FACE ordinal.
CVZB Real-Time Assembler Not Applicable Changed Added multiple fallback extent support.
CWGO Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
CYEP Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CYF1 Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
CYF3 Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
CYF8 Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
CYGN Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CYH0 Real-Time Assembler Not Applicable Changed Updated for changes to PIDT mask usage.
CYH3 Real-Time Assembler Not Applicable Changed Updated to use the SAMXPRO equate value for the maximum number of processors.
CYH4 Real-Time Assembler Not Applicable Changed Updated for changes to PIDT mask usage.
CYPR Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CYPS Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
CYTT Real-Time Assembler Not Applicable Changed Changed for GF control record structure in fixed record type #IBMMP4.
CYYA Real-Time Assembler Not Applicable Changed Updated to call segment CYYK to file CTKC data.
CYYB Real-Time Assembler Not Applicable Changed Removed reference to processor equates in CX0CK, and split #KEYPT support between #KEYPT and #KFBXn fixed file records.
CYYD Real-Time Assembler Not Applicable Changed Split #KEYPT support between #KEYPT and #KFBXn fixed file records.
CYYE Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
CYYF Real-Time Assembler Not Applicable New Adds find and file services for the #CN1ST fixed record type.
CYYG Real-Time Assembler Not Applicable New Provides the parser function for the ZMIGR command parameters.
CYYH Real-Time Assembler Not Applicable New Provides the CTKI function for the ZMIGR command.
CYYJ Real-Time Assembler Not Applicable New Provides the CTKC function for the ZMIGR command and updated for changes to the SIPCC macro interface.
CYYK Real-Time Assembler Not Applicable New Reformats CTKC to 8-way loosely coupled format, if necessary, before filing.
CYYL Real-Time Assembler Not Applicable New Reformats CTKC to 32-way loosely coupled format, if necessary, before completing the find process.
CYYM Real-Time Assembler Not Applicable Changed Updated to call segment CYYL to find CTKC data.
CZXD Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
DCR2 Offline Assembler DCRS Changed Removed CPMXCPU equate.
DRD2 Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.
DRD4 Real-Time Assembler Not Applicable Changed Updated for changes to the SIPCC macro interface.
DYDE Real-Time Assembler Not Applicable Changed Updated for changes to the @@BUSED field in RECOUP DSECT.
DYDI Real-Time Assembler Not Applicable Changed Updated for changes to the 1052 FC33 record.
FTER00 Offline C FCTBG Changed Added support for new fallback extent record types (#KFBXn).
FTGN00 Offline C FCTBG Changed Updated maximum number of processors.
FTVA02 Offline C FCTBG Changed Added support for new fallback extent record types (#KFBXn), and updated RECNO requirements for #KBA and #KSA1 - 8.
FTVA03 Offline C FCTBG Changed Added new INETD and MPIF record types, and added checks for #KFBX0-254 and #RLOG9 - 32.
GOGO Real-Time Assembler Not Applicable Changed Updated for super GOA support.
IPLA Offline Assembler Not Applicable Changed Split #KEYPT support between #KEYPT and #KFBXn fixed file records.
JCD6 Real-Time Assembler Not Applicable Changed Updated to use CYYF to retrieve the #CN1ST fixed record type.
OSTGRT Offline Assembler OSTG Changed Updated for 32-way loosely coupled processor support.
STPP Offline Assembler PPCP Not Changed Reassembled to include changes to data macro CFMDC.
TLDR Offline Assembler TPFLDR Changed Expanded the CPU ID table for 32-way loosely coupled processor support.
XHA3 Real-Time Assembler Not Applicable Changed Updated to allow 32 processors to share the message switching queues.
XLPP Real-Time Assembler Not Applicable Changed Updated IPC base support and user level for 32-way loosely coupled processor support.

System Equates

The following section summarizes system equate changes.

SYSEQ Tags

Table 1209 summarizes changes to equates that are not configuration dependent (in SYSEQ). This information is presented in alphabetic order by the name of the SYSEQ tag.

Table 1209. Changes to SYSEQ Tags for 32-Way Loosely Coupled Processor Support

SYSEQ Tag Equate Value New, Changed, or No Longer Supported?
#CRCRP8 - 31 171 - 194 New
#ICHUTLZ 93 New
#INETDCF_OLD 158 New
#MPIF_MIG1 169 New
#MPIF_MIG2 170 New
#RCPGLB X'1B' - X'39' Changed
#TCPICDT 59 New
#TCPIPCT 58 Changed
#TCPIPCT_OLD 150 New

User Exits

There are no changes.

Functional and Operational Changes

The following section summarizes functional and operational changes. This information is presented in alphabetic order by the functional or operational change.

See Appendix A, "PUT 2-15 Interface Changes by Authorized Program Analysis Report (APAR)" for a summary of functional and operational changes by APAR.

Commands

Table 1210 summarizes command changes. This information is presented in alphabetic order by the name of the command. See TPF Operations for a complete description of all commands.

Attention: Changes to commands can impact any automation programs you are using in your complex.

Table 1210. Changes to Commands for 32-Way Loosely Coupled Processor Support

Command New, Changed, or No Longer Supported? Description of Change
ZCLAW Changed Documentation-only change to identify restrictions on using the command in a loosely coupled complex, which includes processors with and without 32-way loosely coupled processor support.
ZINET ADD Changed Documentation-only change to identify restrictions on using the command in a loosely coupled complex, which includes processors with and without 32-way loosely coupled processor support.
ZINET ALTER Changed Documentation-only change to identify restrictions on using the command in a loosely coupled complex, which includes processors with and without 32-way loosely coupled processor support.
ZINET DELETE Changed Documentation-only change to identify restrictions on using the command in a loosely coupled complex, which includes processors with and without 32-way loosely coupled processor support.
ZKPTR New Provides support for updating keypoint pointer records during system restart and for displaying keypoint pointer records.
ZMIGR New Provides support for migration to 32-way loosely coupled processor support.
ZMPIF Changed Added the ALL subparameter to the PDF INIT parameter option and documentation change to identify restrictions on using the command in a loosely coupled complex, which includes processors with and without 32-way loosely coupled processor support.

Messages and System Errors

Table 1211 summarizes message (offline and online messages) and system error changes.

The message IDs or system error numbers are listed in numeric order preceded by their alphabetic prefix. Some offline and online messages do not have a standard message ID. For these, the messages are presented in alphabetic order based on the initial message text; or for those messages that begin with variable information, the initial message text that follows that variable information. See Messages (System Error and Offline) and Messages (Online) for a complete description of all messages and system errors.

Attention: Changes to offline messages, online messages, and system errors may impact any automation programs you are using in your complex.

Table 1211. Changes to Messages and System Errors for 32-Way Loosely Coupled Processor Support

Message ID or System Error Number Message Type New, Changed, or No Longer Supported?
000074 System Error Changed
0000EE System Error Changed
000296 System Error New
000297 System Error New
000298 System Error New
005100 System Error New
005101 System Error New
005102 System Error New
005103 System Error New
005104 System Error New
005105 System Error New
005106 System Error New
005107 System Error New
005108 System Error New
005109 System Error New
00510A System Error New
00510B System Error New
00510C System Error New
006543 System Error New
007701 System Error Changed
00C13D System Error New
ACPL0104E Online New
ACPL0105W Online New
ACPL0106E Online New
ACPL0107W Online New
B0P00006E Online New
BOF80003I Online No Longer Supported
BOF80008I Online New
BRV30005E Online No Longer Supported
BRV30006E Online No Longer Supported
BRV30008E Online No Longer Supported
BRV30009E Online No Longer Supported
BRV30014E Online New
BRV30015E Online New
BRV30016E Online New
BRV30017E Online New
BRV50005E Online No Longer Supported
BRV50006E Online No Longer Supported
BRV50008E Online No Longer Supported
BRV50009E Online No Longer Supported
BRV50016E Online New
BRV50017E Online New
BRV50018E Online New
BRV50019E Online New
CBG20051I Online New
CBG20052I Online New
CBG20053I Online New
CBG20054I Online New
CBR10001E Online Changed
CBR10002E Online Changed
CBR10003I Online New
CBR10004I Online New
CBY00040E Online Changed
CBY00050E Online Changed
CBY00060E Online Changed
CLAW0001I Online Changed
CLAW0054I Online New
CLAW0055I Online New
CLTR0001I Online Changed
CLTR0006I Online New
CVRQ0001I Online No Longer Supported
CVRQ0003I Online New
CVZ10002I Online New
CVZ10003E Online New
CVZ10004E Online New
CVZ60001A Online New
CVZ60002A Online New
CVZ60003E Online New
CVZ60004I Online New
CVZ60005W Online New
CVZ60006T Online New
DSMG0070E Online Changed
DSMG0072E Online Changed
DSMG0080E Online Changed
DSMG0081E Online Changed
DSMG0090E Online Changed
DSMG0095E Online New
DSMG0096I Online New
DSMG0099E Online New
DSMG0172E Online Changed
FCTB0106I Offline Changed
FCTB0122E Offline New
FCTB0123W Offline New
FMN0015I Online New
FMN0017E Online New
FMNT0018E Online New
IMAG0011I Online No Longer Supported
IMAG0021I Online No Longer Supported
IMAG0211I Online New
IMAG0221I Online New
INET0020I Online New
IPLA0050E Online Changed
IPLA0055W Online New
IPLA0056T Online New
IPLB0003T Online New
IPLB0008T Online New
IPLB0009T Online New
IPLB0013E Online New
IPLB0018W Online New
KPTR0001I Online New
KPTR0002T Online New
KPTR0003I Online New
KPTR0004E Online New
KPTR0005I Online New
KPTR0006E Online New
KPTR0007E Online New
KPTR0010I Online New
KPTR0020I Online New
KPTR0030I Online New
MIGR0001I Online New
MIGR0002I Online New
MIGR0003I Online New
MIGR0004I Online New
MIGR0005T Online New
MIGR0006T Online New
MIGR0007W Online New
MIGR0008T Online New
MIGR0009I Online New
MIGR0010I Online New
MIGR0011I Online New
MIGR0012T Online New
MIGR0013I Online New
MIGR0014I Online New
MIGR0015T Online New
MIGR0016I Online New
MIGR0017T Online New
MIGR0018T Online New
MIGR0019I Online New
MIGR0020T Online New
MIGR0021I Online New
MIGR0022W Online New
MIGR0023E Online New
MIGR0025T Online New
MIGR0030I Online New
MIGR0031I Online New
MIGR0032I Online New
MIGR0033I Online New
MIGR0034E Online New
MIGR0035E Online New
MIGR0036I Online New
MIGR0037E Online New
MIGR0038E Online New
MIGR0039E Online New
MIGR0040I Online New
MIGR0041I Online New
MIGR0042I Online New
MIGR0043I Online New
MIGR0044E Online New
MIGR0045E Online New
MPIF0038E Online Changed
MPIF0054A Online Changed
MPIF0064E Online Changed
MPIF0079A Online Changed
PMIG0015E Online New
PROT0058E Online New
TPLD0125E Online New
TPLD0126E Online New

Performance or Tuning Changes

There are no changes.

Storage Considerations and Changes

There are no changes.

System Initialization Program (SIP) and System Generation Changes

There are no changes.

Loading Process Changes

There are no changes.

Online System Load Changes

There are no changes.

Publication Changes

Table 1212 summarizes changes to the publications in the TPF library. This information is presented in alphabetic order by the publication title. See the TPF Library Guide for more information about the TPF library.

Table 1212. Changes to TPF Publications for 32-Way Loosely Coupled Processor Support

Publication Title Softcopy File Name Description of Change
TPF C/C++ Language Support User's Guide GTPCLU0F Updated with changes to the sipcc and tpf_genlc functions for 32-way loosely coupled processor support.
TPF Concepts and Structures GTPCON0C Updated for 32-way loosely coupled processor support.
TPF Database Reference GTPDBR0D Updated keypoint equates for 32-way loosely coupled processor support.
TPF General Macros GTPGEN0E Updated the GENLC macro for 32-way loosely coupled processor support.
TPF Main Supervisor Reference GTPMSR08 Updated with CTKI changes for 32-way loosely coupled processor support.
Messages (System Error and Offline) and Messages (Online) Not Applicable Updated with information about messages and system errors that were added, changed, and no longer supported for 32-way loosely coupled processor support.
TPF Migration Guide: Program Update Tapes GTPMG205 Updated with migration considerations for 32-way loosely coupled processor support.
TPF Operations GTPOPR0F Updated with information about the commands that were added and changed for 32-way loosely coupled processor support.
TPF System Generation GTPSYG0F Updated macro record types for 32-way loosely coupled processor support.
TPF System Installation Support Reference GTPINR0F Updated macro record types for 32-way loosely coupled processor support.
TPF System Macros GTPSYS0F Updated the SIPCC macro for 32-way loosely coupled processor support.
TPF Transmission Control Protocol/Internet Protocol GTPCLW0B Updated the Internet daemon (INETD) and CLAW device table (CDT) for 32-way loosely coupled processor support.

Host System Changes

There are no changes.

Application Programming Interface (API) Changes

The following macros and functions have been enhanced:

Database Changes

There are no changes.

Feature Changes

There are no changes.

Installation Validation

There are no changes.

Migration Scenarios

Before you begin your migration to 32-way loosely coupled processor support, read Functional Overview and Architecture, paying particular attention to Coexistence and Migration and Fallback.

To Migrate Your Complex to 32-Way Loosely Coupled Processor Support

Before You Begin

  • If you need to fall back to the previous level of support during the installation and migration to 32-way loosely coupled processor support, follow the procedure in Falling Back from 32-Way Loosely Coupled Processor Support.
  • You need to examine the code, make the necessary modification, reassemble or recompile, and link-edit any application that uses the following functions:
    • Interprocessor communication (IPC)
    • IC0CK (c$ic0ck.h)
    • CN1ST
    • PI1DT (c$pi1dt.h).

    See Coexistence and Migration and Fallback for more information about modifications to your applications required by 32-way loosely coupled processor support.

    Note:
    32-way loosely coupled processor support must be installed on the processor that is used to assemble, compile, or link-edit applications modified to run in a loosely coupled complex with more than eight processors.

  1. Install PUT 15, which contains APAR PJ27785 for 32-way loosely coupled processor support, on your TPF 4.1 system.
  2. Update the data record information library (DRIL) with the global storage allocation record fields:
    • GO2DSP
    • GO2CEC
    • GO2CID
    • GO2IID
    • GO2IS.

    See the GO1GO data macro for more information about the global fields and see TPF Program Development Support Reference for more information about DRIL.

  3. Update the SIP RAMFIL macro input statements to the FACE table generator (FCTBG):
    • Add RAMFIL statements, specifying the following new record types in the RECID parameter:
      • #CN1ST
      • #DSCRU
      • #HDREC
      • #IDCF1
      • #KFBXnnn
      • #PDREU
      • #SONRPEx.
    • Modify the RAMFIL statements for the following fixed file record types:
      • #BRIDCOR
      • #IBMMP4
      • #IBMMS
      • #KBA
      • #KSA1 - 8
      • #RC8RFS.

    Make sure that the required number of ordinals is specified. See TPF System Generation and Table 1069 for more information about fixed file record types; see TPF System Generation for more information about the RAMFIL macro.

  4. Update SIP stage 1 deck as follows:
    • Add the CTKI32LC parameter to CONFIG macro (set to NO)
    • Add the CTKC32LC parameter to CRASTB macro (set to NO).

    See TPF System Generation for more information about the CONFIG and CRASTB macros.

  5. Run the FCTBG to create a new FACE table.
  6. Assemble the SIP stage I deck to create a SIP stage II deck.
  7. Run the system allocator program (SALO) using the IBMPAL and SPPGML additions for the newly created segments to create an updated program allocation table (IPAT) and a system allocator table (SAL).
  8. Run SIP stage II.
  9. Deactivate each processor and IPL it from an image containing 32-way loosely coupled processor support.
    Note:
    During the first IPL of the first processor from image containing 32-way loosely coupled processor support, the TPF system will display messages IPLA0050E and IPLA0055W for the BSS and messages IPLB0018W and IPLB0086E for all other subsystems. These messages are displayed because the new keypoint pointer records have not been initialized on the subsystems. Because this is an expected occurrence and temporary pointer records will be used, continue with the IPL.

    During restart, message CVZ60001A is displayed for each subsystem being IPLed. This message will request the operator to enter the ZKPTR command. Enter the ZKPTR REPLACE command for each subsystem to initialize the keypoint pointer records. This must be done only once on the first processor to be IPLed with 32-way loosely coupled processor support.

  10. If you operate the loosely coupled complex in a coexistence mode with some processors IPLed from images with 32-way loosely coupled processor support and other processors IPLed with images without 32-way loosely coupled processor support, you must observe the following restrictions:
    • Before running recoup, you must enter the ZMIGR command with the RECOUP and INIT parameters specified to initialize the new FC33 records. All processors participating in a recoup run must be at the same PUT level.
    • While the loosely coupled complex is operating in coexistence mode, restrict your use of the following commands:
      • ZMPIF DEFINE DEVICE
      • ZMPIF DEFINE PATH
      • ZINET DISPLAY
      • ZINET ADD
      • ZINET ALTER.

      See Coexistence, Migration and Fallback, and TPF Operations for more information about any restrictions and the use of these commands.

  11. Once all active processors in the loosely coupled complex are IPLed from images containing 32-way loosely coupled processor support, do the following:
    1. Confirm that any necessary modifications have been made to your applications and that the applications have been reassembled, recompiled, and link-edited.
    2. Enter the ZMIGR command with the PROCESSOR and STATUS parameters specified to confirm that all processors are at the same PUT level.
    3. Migrate to 32-way loosely coupled processor support for recoup by doing the following:
      1. If you have not done so previously, enter the ZMIGR command with the RECOUP and INIT parameters specified to initialize the new FC33 records.
      2. Enter the ZMIGR command with the RECOUP and CONVERT parameters specified to complete the recoup data conversion and movement.

      These commands must be entered on each multiple database function (MDBF) subsystem, but need to be entered on only one processor in the complex.

    4. Migrate to 32-way loosely coupled processor support for CTKI by entering the ZMIGR command with the CTKI and CONVERT parameters specified to convert CTKI data to 32-way loosely coupled format. This command must be entered on the basic subsystem (BSS) and needs to be entered on only one processor in the complex.
    5. Migrate to 32-way loosely coupled processor support for CTKC by entering the ZMIGR command with the CTKC and CONVERT parameters specified to convert CTKC data to 32-way loosely coupled format. This command must be entered on the BSS and needs to be entered on only one processor in the complex.
    6. Migrate to 32-way loosely coupled processor support for keypoint access by entering the ZMIGR command with the KEYPOINT and CONVERT parameters specified to convert keypoint data to 32-way loosely coupled format and location. This command must be entered on each MDBF subsystem, but needs to be entered on only one processor in the complex.
    7. Migrate to 32-way loosely coupled processor support for MPIF by entering the ZMIGR command with the MPIF and CONVERT parameters specified to convert MPIF data to 32-way loosely coupled format. This command must be entered on the BSS and needs to be entered on only one processor in the complex.
      Note:
      Enter the ZMIGR command with the MPIF parameter specified only if you have the MPIF feature installed on your TPF 4.1 system.
    8. Migration of the general file control record (GFCR) is performed automatically by the TPF 4.1 system. To change the definition of the GFCR, you may load a new keypoint B, which indicates that the GFCR should be initialized using the premount information in segment CVZD. See General File for more information about automatic migration of the GFCR and see TPF Database Reference for more information about general files and the GFCR.
    9. Migration of the general data set (GDS) restart control records (RCRs) is performed automatically by the TPF 4.1 system. You may request that the premount information in segments CVZE and CVZF be used to initialize the RCRs by using the ZDSMG INIT command. See General Data Set (GDS) for more information about automatic migration of the RCRs and see TPF Operations for more information about the ZDSMG INIT command.

Notes:

  1. Once you have completed migration to recoup, CTKI, CTKC, keypoint, and MPIF support for 32-way loosely coupled processors by converting records and data, any processors added to the loosely coupled complex must be running 32-way loosely coupled processor support. If there is a requirement for a processor that is not running 32-way loosely coupled processor support to join the loosely coupled complex, you must perform the fallback procedure defined in Falling Back from 32-Way Loosely Coupled Processor Support.

  2. Once the records and data have been converted, make sure that the CTKI32LC parameter of the CONFIG macro and the CTKC32LC parameter of the CRASTB macro in your system generation input are set to YES so that CTKI and CTKC are generated correctly for any new TPF 4.1 systems.

  3. If you have not completed the conversion to 32-way loosely coupled pool support, that is, the ZPMIG CONVERT command has not been entered and all pool structures are still in PXP format, you must complete the conversion to 32-way loosely coupled pool support before you can define more than 8 loosely coupled processors in your TPF complex. See 32-Way Loosely Coupled Pool Support (APAR PJ27686) for more information about 32-way loosely coupled pool support.

  4. See Migration and Fallback and TPF Operations for more information about the data being converted and the use of the commands.

Once migration to 32-way loosely coupled processor support is completed and there is no requirement to fall back to coexistence mode, do the following:

You can now add processors 9 - 32 to the TPF 4.1 loosely coupled processor complex.

Falling Back from 32-Way Loosely Coupled Processor Support

Before You Begin

Once you have generated the ninth processor for the loosely couple complex, it is no longer possible to fall back to a TPF 4.1 system without 32-way loosely coupled processor support.

If you must IPL a processor without 32-way loosely coupled processor support in the loosely coupled complex, do the following:

  1. Enter the ZMIGR command with the RECOUP and FALLBACK parameters specified to restore the recoup data and record format and locations.
  2. Enter the ZMIGR command with the CTKI and FALLBACK parameters specified to restore the CTKI records and data format.
  3. Enter the ZMIGR command with the CTKC and FALLBACK parameters specified to restore the CTKC data format.
  4. Enter the ZMIGR command with the KEYPOINT and FALLBACK parameters specified to restore keypoint data format and location.
  5. Enter the ZMIGR command with the MPIF and FALLBACK parameters specified to restore the MPIF records and data format.
    Note:
    Enter the ZMIGR command with the MPIF parameter specified only if you have the MPIF feature installed on your TPF 4.1 system.
  6. On each processor that is to be IPLed with a back-level TPF 4.1 system, you must enter the ZPSMS command with the PR and DEAC parameters specified to reset the flag that indicates that the processor is migrated. Otherwise, IPC on the migrated processors will continue to attempt to communicate with that processor using the 32-way loosely coupled format.
  7. If you have defined and loaded super GOA records for 32-way loosely coupled processor support, you must restore the previous super GOA records by entering the ZSLDR command to load the previous PILOTA tape.

Notes:

  1. Fallback must be performed for all functions.

  2. For those functions that required you to enter the ZMIGR command with the CONVERT parameter specified for each MDBF subsystem, you must also enter ZMIGR command with the FALLBACK parameter specified for each MDBF subsystem.

  3. If you generate any new TPF 4.1 systems when ZMIGR FALLBACK processing is completed, make sure that the CTKI32LC parameter of the CONFIG macro and the CTKC32LC parameter of the CRASTB macro in your system generation input are set to NO so that CTKI and CTKC correctly reflect that the data structures and content are back-level. When you migrate back to 32-way loosely coupled processor support again, set the CTKI32LC and CTKC32LC parameters to YES.

  4. There is no fallback action required for general file or general data set support. Any TPF 4.1 system image that does not contain 32-way loosely coupled processor support will automatically use the general file control record (GFCR) in the #IBMM4 record type and the general data set restart control records (RCRs) in the #DSCRI record type. The previous GFCR and RCRs will not contain any changes to the GFCR and RCRs in the #IBMMP4 and #DSCRU record types made by general file and general data set support running on TPF 4.1 system images with 32-way loosely coupled processor support.